公开(公告)号：US20070271445A1

公开(公告)日：2007-11-22

申请号：US11832777

申请日：2007-08-02

申请人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry

IPC分类号： G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：US20070226464A1

公开(公告)日：2007-09-27

申请号：US11277735

申请日：2006-03-28

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F9/40

CPC分类号： G06F9/30145 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3897

摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.

摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

公开(公告)号：US07168076B2

公开(公告)日：2007-01-23

申请号：US10194911

申请日：2002-07-12

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3842 ,  G06F9/3851

摘要： One embodiment of the present invention provides a system that facilitates efficient join operations between a head thread and a speculative thread during speculative program execution, wherein the head thread executes program instructions and the speculative thread executes program instructions in advance of the head thread. The system operates by executing a primary version of a program using the head thread, and by executing a speculative version of the program using the speculative thread. When the head thread reaches a point in the program where the speculative thread began executing, the system performs a join operation between the head thread and the speculative thread. This join operation causes the speculative thread to act as a new head thread by switching from executing the speculative version of the program to executing the primary version of the program. To facilitate this switching operation, the system performs a lookup to determine where the new head thread is to commence executing within the primary version of the program based upon where the speculative thread is currently executing within the speculative version of the program.

摘要翻译： 本发明的一个实施例提供了一种在推测程序执行期间有助于头螺纹和推测螺纹之间的有效连接操作的系统，其中头螺纹执行程序指令，并且推测螺纹在头螺纹之前执行程序指令。 该系统通过使用头部线程执行程序的主要版本，并使用推测性线程执行程序的推测版本来进行操作。 当头线到达推测线程开始执行的程序中的一个点时，系统将在头线程和推测线程之间执行连接操作。 此连接操作通过从执行程序的推测版本切换到执行程序的主要版本而使推测线程充当新的头线程。 为了促进这种切换操作，系统执行查找，以基于推测线程当前在程序的推测版本中执行的位置来确定新的头线程将在程序的主版本内开始执行的位置。

公开(公告)号：US07152232B2

公开(公告)日：2006-12-19

申请号：US10194856

申请日：2002-07-12

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/46

CPC分类号： G06F9/544

摘要： One embodiment of the present invention provides a system that facilitates inter-processor communication and synchronization through a hardware message buffer, which includes a plurality of physical channels that are structured as queues for communicating between processors in a multiprocessor system. The system operates by receiving an instruction to perform a data transfer operation through the hardware message buffer, wherein the instruction specifies a virtual channel to which the data transfer operation is directed. Next, the system translates the virtual channel into a physical channel, and then performs the data transfer operation on the physical channel within the hardware message buffer. In one embodiment of the present invention, if the data transfer operation is a store operation and the physical channel is already full, the system returns status information indicating that the physical channel is too full to perform the store operation. In one embodiment of the present invention, if the data transfer operation is a load operation and the physical channel is empty, the system returns status information indicating that the physical channel is empty and the load operation cannot be completed.

公开(公告)号：US20060200632A1

公开(公告)日：2006-09-07

申请号：US11399049

申请日：2006-04-06

申请人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry ,  Mark Moir ,  Maurice Herlihy

发明人： Marc Tremblay ,  Quinn Jacobson ,  Shailender Chaudhry ,  Mark Moir ,  Maurice Herlihy

IPC分类号： G06F12/14

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F12/0862

摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.

公开(公告)号：US20060010309A1

公开(公告)日：2006-01-12

申请号：US11058522

申请日：2005-02-14

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. During normal-execution mode, the processor issues instructions for execution in program order. When the processor encounters a long-latency operation, such as a load miss, the processor records the long-latency operation in a long-latency scoreboard, wherein each entry in the long-latency scoreboard includes a deferred buffer start index. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order. Upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the processor updates a deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction. When a long-latency operation returns, the processor executes instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.

摘要翻译： 本发明的一个实施例提供一种在支持推测执行的处理器中返回长延迟操作之后选择性地执行延迟指令的系统。 在正常执行模式下，处理器以程序顺序发出执行指令。 当处理器遇到诸如加载未命中的长延迟操作时，处理器将长延迟操作记录在长延迟记分板中，其中长延迟记分板中的每个条目包括延迟缓冲器开始索引。 在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟到延迟缓冲器中，并且其中 其他非延迟指令按程序顺序执行。 在遇到取决于长延迟记分板中的长时间延迟操作的延迟指令时，处理器更新与长延迟操作相关联的延迟缓冲器开始索引以指向由延迟指令占用的延迟缓冲器中的位置。 当长延迟操作返回时，处理器执行延迟缓冲区中的指令，从延迟缓冲区起始索引开始，用于返回长延迟操作。

公开(公告)号：US20050262301A1

公开(公告)日：2005-11-24

申请号：US11189591

申请日：2005-07-25

申请人： Quinn Jacobson ,  Marc Tremblay ,  Shailender Chaudhry

发明人： Quinn Jacobson ,  Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

摘要： One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

摘要翻译： 本发明的一个实施例提供了一种在事务执行期间有助于延迟来自其他线程的干扰存储器访问的系统。 在一个指令块的事务执行期间，系统从另一个线程（或处理器）接收到执行涉及高速缓存线的存储器访问的请求。 如果执行高速缓存行上的存储器访问将干扰事务执行，并且如果可以延迟存储器访问，则系统延迟存储器访问并存储用于高速缓存行的复制信息以使得能够复制高速缓存行 回到请求线程。 在稍后的时间，当内存访问不再干扰事务执行时，系统执行内存访问并将缓存行复制回请求的线程。

公开(公告)号：US20050251666A1

公开(公告)日：2005-11-10

申请号：US10923219

申请日：2004-08-20

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instructions in a speculative-execution mode. The system also maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.

摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免写后读取（RAW）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到停顿状态时，系统生成检查点，并以推测执行模式执行指令和后续指令。 该系统还维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 系统使用这种依赖信息来避免在推测执行模式下的RAW危害。

公开(公告)号：US06934809B2

公开(公告)日：2005-08-23

申请号：US10080859

申请日：2002-02-22

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F12/0862 ,  G06F2212/6028

摘要： Techniques have been developed whereby likely pointer values are identified at runtime and contents of corresponding storage location can be prefetched into a cache hierarchy to reduce effective memory access latencies. In some realizations, one or more writable stores are defined in a processor architecture to delimit a portion or portions of a memory address space.

摘要翻译： 已经开发了技术，其中可能在运行时识别指针值，并且可以将对应的存储位置的内容预取到高速缓存层级以减少有效的存储器访问延迟。 在一些实现中，在处理器架构中定义一个或多个可写存储器以限定存储器地址空间的一部分或部分。

公开(公告)号：US20050081195A1

公开(公告)日：2005-04-14

申请号：US10686061

申请日：2003-10-14

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中其他非延迟指令以程序顺序执行。