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公开(公告)号：US07353363B2
公开(公告)日：2008-04-01
申请号：US11277716
申请日：2006-03-28
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/30196 , G06F9/328 , G06F9/382 , G06F9/3857 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, between fixed decode and programmable decode paths provided by a processor. In this way, a patchable and/or programmable decode mechanism can be efficiently provided. In some realizations, either (or both) predecode or (and) decode may be configured or reconfigured post-manufacture. In some realizations, either (or both) predecode or (and) decode may be configured at (or about) initialization. In some realizations, either (or both) predecode or (and) decode may be configured at run-time.
摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现，可以采用可配置的预解码机制来针对相应的指令模式在由处理器提供的固定解码和可编程解码路径之间进行选择。 以这种方式，可以有效地提供可修补和/或可编程的解码机制。 在一些实现中，可以在制造后配置或重新配置（或两者）预解码或（和）解码。 在某些实现中，可以在（或约）初始化时配置（或两者）预解码或（和）解码。 在某些实现中，可以在运行时配置（或两者）预解码或（和）解码。
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公开(公告)号：US20070226464A1
公开(公告)日：2007-09-27
申请号：US11277735
申请日：2006-03-28
IPC分类号： G06F9/40
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。
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公开(公告)号：US07509481B2
公开(公告)日：2009-03-24
申请号：US11277735
申请日：2006-03-28
IPC分类号： G06F9/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译： 已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。 特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。 例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。 可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。 类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。 在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。 在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。
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4.发明授权公开(公告)号：US07836290B2
公开(公告)日：2010-11-16
申请号：US11363625
申请日：2006-02-28
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F9/3863 , G06F9/3867
摘要： A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.
摘要翻译： 一种技术恢复返回地址堆栈（RAS）内容，并恢复RAS堆栈顶部（TOS）指针的对齐，用于由于推测操作，无序指令处理和异常处理引起的错误预测。 在本发明的至少一个实施例中，一种装置包括推测执行处理器流水线，用于在流水线的第一阶段保持相对于指令流的返回地址的第一结构，用于维持相对于指令流的返回地址的至少第二结构 在管道的第二阶段。 管道的第二阶段比第一阶段管道更深。 该装置包括可操作以至少将从第二结构返回地址再现到第一结构的电路。
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5.发明授权Logical power throttling of instruction decode rate for successive time periods 有权连续时间段的逻辑功率节制指令解码速率公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
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6.发明授权Start transactional execution (STE) instruction to support transactional program execution 有权启动事务执行（STE）指令以支持事务性程序执行公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译： 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。
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公开(公告)号：US07418577B2
公开(公告)日：2008-08-26
申请号：US10637169
申请日：2003-08-08
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
摘要翻译： 本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。 在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。 如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。
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公开(公告)号：US20070226467A1
公开(公告)日：2007-09-27
申请号：US11425869
申请日：2006-06-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译： 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。
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公开(公告)号：US20120331314A1
公开(公告)日：2012-12-27
申请号：US13529761
申请日：2012-06-21
IPC分类号： G06F1/32
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。
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10.发明授权公开(公告)号：US07818510B2
公开(公告)日：2010-10-19
申请号：US11832777
申请日：2007-08-02
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815
摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.
摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。
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