公开(公告)号：US5881071A

公开(公告)日：1999-03-09

申请号：US812286

申请日：1997-03-06

申请人： Alexander Kuznetsov ,  Masuo Umemoto ,  Naoya Kobayashi ,  Hideki Sawaguchi

发明人： Alexander Kuznetsov ,  Masuo Umemoto ,  Naoya Kobayashi ,  Hideki Sawaguchi

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M13/25 ,  G06F11/00

CPC分类号： G11B20/10009 ,  G11B20/1833

摘要： A digital write-and-read method and a signal processing apparatus wherein a write encoder includes a bit distribution circuit for dividing an input data block into n (n: 2 or more) series of bit strings and outputting them in parallel, a first coding circuit for executing predetermined coding for each of data series so distributed and a second coding circuit for converting the output bit series D1 to D3 of the first coding circuit to an n-bit channel code by looking up the previous channel code information, and wherein the second coding circuit executes coding by using a combination having a large Euclidean distance in a partial response equalization output taking inter-symbol interference of at least three bits into consideration as a pair.

摘要翻译： 一种数字写入读取方法和信号处理装置，其中写入编码器包括一个位分配电路，用于将输入数据块分成n（n：2或更多）个位串并将它们并行输出;第一编码 用于对分配的数据序列中的每一个执行预定编码的电路和用于通过查找先前的信道码信息将第一编码电路的输出比特串D1至D3转换为n比特信道码的第二编码电路，并且其中， 第二编码电路在部分响应均衡输出中使用具有较大欧几里德距离的组合来执行编码，以至少考虑三比特的符号间干扰作为一对。

公开(公告)号：US5594756A

公开(公告)日：1997-01-14

申请号：US492616

申请日：1995-06-20

申请人： Wataru Sakurai ,  Hideki Sawaguchi ,  Naoki Satoh ,  Masuo Umemoto

发明人： Wataru Sakurai ,  Hideki Sawaguchi ,  Naoki Satoh ,  Masuo Umemoto

IPC分类号： G11B20/10 ,  H04B1/10 ,  H04B3/06 ,  H04B3/08 ,  H04L25/03 ,  H03H7/30

CPC分类号： H04L25/03057 ,  G11B20/10009 ,  G11B20/10046

摘要： A decision feedback equalization circuit which can be operated at a high speed with a low cost as well as a high-speed digital data communication system and a high-speed digital data recording system using the equalization circuit are disclosed. The decision feedback equalization circuit has data memories which correspond to the number of available values in decision result and in which feedback signals corresponding to all the next decision results are previously prepared as candidates so that a suitable one of the feedback signal candidates is selected and fed back based on the obtained decision result, thus realizing high-speed operation of a feedback loop.

摘要翻译： 公开了一种能够以低成本高速运行的判决反馈均衡电路以及使用均衡电路的高速数字数据通信系统和高速数字数据记录系统。 判决反馈均衡电路具有数据存储器，其对应于判定结果中可用值的数量，并且其中预先对应于所有下一个判定结果的反馈信号作为候选，使得选择并馈送合适的一个反馈信号候选 基于获得的决策结果，从而实现反馈回路的高速运行。

公开(公告)号：US07436611B2

公开(公告)日：2008-10-14

申请号：US11377367

申请日：2006-03-17

申请人： Yasutaka Nishida ,  Takehiko Hamaguchi ,  Hideki Sawaguchi ,  Hisashi Takano

发明人： Yasutaka Nishida ,  Takehiko Hamaguchi ,  Hideki Sawaguchi ,  Hisashi Takano

IPC分类号： G11B5/09 ,  G11B5/596

CPC分类号： G11B5/59655 ,  G11B5/59688

摘要： In a method of servo writing of a magnetic recording system and the magnetic recording system, the signal is recorded in a dummy area with a higher recording density than the burst signal. Also, the maximum bit length of the burst area is shortened as compared with the maximum bit length of the data area. A servo control method for perpendicular recording similar to that for longitudinal recording can be used to reduce the development cost. The anti-signal decay performance is also improved. Further, since the variations of the burst signal along the track width is suppressed, the positioning accuracy is improved. These effects combine to produce a reliable magnetic recording system of large capacity.

摘要翻译： 在磁记录系统和磁记录系统的伺服写入的方法中，该信号被记录在具有比突发信号更高的记录密度的虚拟区域中。 此外，与数据区域的最大位长度相比，突发区域的最大位长度被缩短。 可以使用与纵向记录类似的垂直记录的伺服控制方法来降低开发成本。 反信号衰减性能也得到提高。 此外，由于抑制了沿着磁道宽度的突发信号的变化，因此提高了定位精度。 这些效应相结合，产生了可靠的大容量磁记录系统。

公开(公告)号：US07076721B2

公开(公告)日：2006-07-11

申请号：US10693970

申请日：2003-10-28

申请人： Hideki Sawaguchi

发明人： Hideki Sawaguchi

IPC分类号： H03M13/29

CPC分类号： G11B20/10055 ,  G11B20/10009

摘要： The present invention discloses an information processing method including the following steps: (1) a first step receiving an encoded information data series as input; (2) a second step selecting a candidate decoded data code series from a first candidate decoded data code series group, decoding the encoded information data series, and generating a first decoded data code series; (3) a third step detecting a position and contents of erroneous decoded data codes in the first decoded data code series that cannot exist in the information data code; (4) a fourth step correcting the erroneous decoded data code and generating a corrected data code; (5) a fifth step selecting a single decoded data code series out of a second candidate decoded data code series group, decoding the encoded information data code series again, and generating a second decoded data code series; (6) The second candidate decode data code series group includes candidate decoded data code series from the first candidate decoded data code series group that fulfills at least one of the following conditions: 1. A candidate decoded data code series that does not contain erroneous decoded data codes that were detected at the third step and that could not be corrected at the fourth step. 2. A candidate data code series that contains: data codes that were determined at the third step to not contain erroneous decoded data codes; and corrected data codes corrected at the fourth step.

摘要翻译： 本发明公开了一种信息处理方法，包括以下步骤：（1）接收编码信息数据序列作为输入的第一步骤; （2）第二步骤，从第一候选解码数据码序列组中选择候选解码数据码序列，解码编码信息数据序列，并生成第一解码数据码序列; （3）检测在信息数据代码中不存在的第一解码数据码序列中的错误解码数据码的位置和内容的第三步骤; （4）第四步骤，校正错误解码的数据代码并产生校正的数据代码; （5）第五步骤，从第二候选解码数据码序列组中选择单个解码数据码序列，再次对编码信息数据码序列进行解码，并生成第二解码数据码序列; （6）第二候选解码数据码序列组包括满足以下条件中的至少一个条件的来自第一候选解码数据码序列组的候选解码数据码序列：1.不包含错误解码的候选解码数据码序列 在第三步检测到并且在第四步无法纠正的数据代码。 2.一种候选数据码系列，包括：在第三步确定的数据码不包含错误的解码数据码; 以及在第四步骤中校正的校正数据代码。

公开(公告)号：US07075743B2

公开(公告)日：2006-07-11

申请号：US09924762

申请日：2001-08-09

申请人： Yasutaka Nishida ,  Takehiko Hamaguchi ,  Hideki Sawaguchi ,  Hisashi Takano

发明人： Yasutaka Nishida ,  Takehiko Hamaguchi ,  Hideki Sawaguchi ,  Hisashi Takano

IPC分类号： G11B5/09

CPC分类号： G11B5/59655 ,  G11B5/59688

摘要： In a method of servo writing of a magnetic recording system and the magnetic recording system, the signal is recorded in a dummy area with a higher recording density than the burst signal. Also, the maximum bit length of the burst area is shortened as compared with the maximum bit length of the data area. A servo control method for perpendicular recording similar to that for longitudinal recording can be used to reduce the development cost. The anti-signal decay performance is also improved. Further, since the variations of the burst signal along the track width is suppressed, the positioning accuracy is improved. These effects combine to produce a reliable magnetic recording system of large capacity.

公开(公告)号：US20060132957A1

公开(公告)日：2006-06-22

申请号：US11354912

申请日：2006-02-16

申请人： Takehiko Hamaguchi ,  Atsushi Nakamura ,  Yasutaka Nishida ,  Masafumi Mochizuki ,  Hideki Sawaguchi

发明人： Takehiko Hamaguchi ,  Atsushi Nakamura ,  Yasutaka Nishida ,  Masafumi Mochizuki ,  Hideki Sawaguchi

IPC分类号： G11B5/02

CPC分类号： G11B5/6005 ,  G11B5/012 ,  G11B5/105 ,  G11B5/127 ,  G11B5/1272 ,  G11B5/2654 ,  G11B5/4886 ,  G11B5/56 ,  G11B2005/001 ,  G11B2005/0021

摘要： A magnetic disk apparatus including: a disk holding data as magnetic information on a magnetic recording film; a head to perform writing and reading of the magnetic information; a rotary actuator to move the head in a radial direction of the disk; plural heat elements in the head to locally heat the disk; a write element in the head to apply a magnetic field to the disk; and means for selecting at least one heat element from the plural heat elements, wherein the means for selecting the heat element selects at least one heat element from the plural heat elements so as to bring a center line of an area heated by the heat element and a center line of the position of the magnetic field generated by the write element into approximate correspondence, in correspondence with a relative angle between the head and a direction of movement of the disk.

公开(公告)号：US07046745B2

公开(公告)日：2006-05-16

申请号：US09986925

申请日：2001-11-13

申请人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

发明人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

IPC分类号： H03D1/00 ,  H04B1/10 ,  G11B1/035

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009 ,  H04L1/0054

摘要： In a data demodulating method, predetermined input data is demodulated based upon a response characteristic of the partial response class 4; the demodulated input data is discrete-filtered to thereby produce filtering data; and the filtering data is maximum likelihood-decoded to thereby produce asymmetrical response data. Further, a magnetic recording/reproducing apparatus is arranged by using this data demodulating method.

摘要翻译： 在数据解调方法中，基于部分响应等级4的响应特性来解调预定输入数据; 解调输入数据被离散滤波，从而产生滤波数据; 并且滤波数据被最大似然解码，从而产生非对称响应数据。 此外，通过使用该数据解调方法来布置磁记录/再现装置。

公开(公告)号：US06873665B2

公开(公告)日：2005-03-29

申请号：US09887328

申请日：2001-06-25

申请人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

发明人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

IPC分类号： G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03M13/09 ,  H03M13/23 ,  H03M13/41 ,  H04L25/03 ,  H04L25/08 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/6331 ,  G11B20/10 ,  G11B20/18 ,  H03M13/09 ,  H03M13/41 ,  H03M13/4115 ,  H03M13/4184 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6505 ,  H04L25/03178

摘要： A digital magnetic recording/reproducing apparatus includes an LVA (List Viterbi Algorithm) detector which produces first to nth best sequences (n>1) of a decoded result, and replaces a likelihood ratio and a path memory of the ith best sequence (i=2, 3, . . . , n) with those of the (2i−1)th best sequence when contents of path memories of the (i−1)th and ith best sequences are equal to each other and an absolute value of a difference between likelihood ratios of the (i−1)th and (2i−1)th best sequences is smaller than a decision threshold. Alternatively, the LVA detector initializes a likelihood ratio of the ith best sequence to be a likelihood ratio of the (i−1)th best sequence with a constant difference value added thereto when contents of path memories of the (i−1)th and ith best sequences are equal to each other.

摘要翻译： 一种数字磁记录/重放装置包括一个产生解码结果的第n至第n个最佳序列（n> 1）的LVA（List Viterbi Algorithm）检索器，并将第i个最佳序列（i = 2，3，...，n）与（i-1）和第i个最佳序列的路径存储器的内容彼此相等时的（2i-1）最佳序列的那些，绝对值 （i-1）和（2i-1）最佳序列的似然比之间的差异小于判定阈值。 或者，LVA检测器将第（i-1）个最佳序列的似然比初始化为第（i-1）个最佳序列的似然比，并且当第（i-1）和 最好的序列彼此相等。

公开(公告)号：US06725418B2

公开(公告)日：2004-04-20

申请号：US09994062

申请日：2001-11-27

申请人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

发明人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

IPC分类号： H03M1341

CPC分类号： G11B20/10296 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343 ,  H03M13/6502

摘要： A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68. A storing element block output circuit 64 and storing element block output terminals 65(1) to 65(D) are provided in each of the storing element blocks 60(1) to 60(D) so that a path memory circuit output 67 may be outputted through an OR circuit 66.

摘要翻译： 布置最大似然解码电路，通过维特比算法的效果来降低功耗。 在同一时间点垂直定位并用于存储每个状态幸存者路径信息的多个存储元件61a至61h以对应于组合的方式被视为存储元件块60（1）至60（D） 状态）的代码间干扰。 存储元件61a至61h的输出通过路径历史选择电路62a至62h再次应用于包含在相同存储元件块中的相应存储元件的输入。 存储元件块60（1）〜（D）中的每一个在每个处理时间点的接收信号的输入定时通过起始点（指针）63（1）至63（D）从起始点 信号（指针）产生电路68.存储元件块输出电路64和存储元件块输出端子65（1）至65（D）中的每一个都设置在每个存储元件块60（1）至60（D）中，使得 可以通过OR电路66输出路径存储器电路输出67。

公开(公告)号：US06668349B1

公开(公告)日：2003-12-23

申请号：US09549929

申请日：2000-04-14

申请人： Hideki Sawaguchi

发明人： Hideki Sawaguchi

IPC分类号： G11B2018

CPC分类号： G11B20/10055 ,  G11B20/10009

摘要： The present invention discloses an information processing method including the following steps: (1) a first step receiving an encoded information data series as input; (2) a second step selecting a candidate decoded data code series from a first candidate decoded data code series group, decoding the encoded information data series, and generating a first decoded data code series; (3) a third step detecting a position and contents of erroneous decoded data codes in the first decoded data code series that cannot exist in the information data code; (4) a fourth step correcting the erroneous decoded data code and generating a corrected data code; (5) a fifth step selecting a single decoded data code series out of a second candidate decoded data code series group, decoding the encoded information data code series again, and generating a second decoded data code series; (6) The second candidate decode data code series group includes candidate decoded data code series from the first candidate decoded data code series group that fulfills at least one of the following conditions: 1. A candidate decoded data code series that does not contain erroneous decoded data codes that were detected at the third step and that could not be corrected at the fourth step. 2. A candidate data code series that contains: data codes that were determined at the third step to not contain erroneous decoded data codes; and corrected data codes corrected at the fourth step.

摘要翻译： 本发明公开了一种信息处理方法，包括以下步骤：（1）接收编码信息数据序列作为输入的第一步骤;（2）从第一候选解码数据码序列组中选择候选解码数据码序列的第二步骤 对编码信息数据序列进行解码，生成第一解码数据码序列;（3）检测在信息数据码中不存在的第一解码数据码序列中的错误解码数据码的位置和内容的第三步骤; 4）校正错误解码数据码并生成校正数据码的第四步骤;（5）从第二候选解码数据码序列组中选择单个解码数据码序列的第五步骤，再次对编码信息数据码序列进行解码 ，并生成第二解码数据码序列;（6）第二候选解码数据码序列组包括来自第一候选解码的候选解码数据码序列 满足以下条件之一的数据编码系列组：1。 候选解码数据码系列，其不包含在第三步骤检测到并且在第四步骤中无法校正的错误解码数据码。 一种候选数据码系列，包括：在第三步骤确定的数据码不包含错误的解码数据码; 以及在第四步骤中校正的校正数据代码。