公开(公告)号：US06320916B1

公开(公告)日：2001-11-20

申请号：US09185097

申请日：1998-11-03

申请人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

发明人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

IPC分类号： H03D100

CPC分类号： H03M13/6331 ,  G11B20/10 ,  G11B20/18 ,  H03M13/09 ,  H03M13/41 ,  H03M13/4115 ,  H03M13/4184 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6505 ,  H04L25/03178

摘要： A digital magnetic recording/reproducing apparatus that has an LVA detector, and that is able to maintain the coding rate as high as {fraction (8/9)} or more, and record at a higher density than in the prior art, wherein, in order that the data sequences up to the (2n−1)th best sequence (n>1) are obtained in the order of higher likelihood ratios, and that. the candidates of those data sequences can be produced, the LVA detector has provided therein a unit which replaces the likelihood ratio and path memory of the ith best sequence by those of the (2i−1)th best sequence when the contents of the (i−1)th path memory coincide with those of the ith path memory (i=2, 3, . . . , n) and the absolute value of the likelihood ratio difference between the (i−1)th best sequence and the (2i−1)th best sequence is smaller than a decision threshold, or a unit which initializes the likelihood ratio of the ith best sequence to be a constant difference value added to the likelihood ratio of the (i−1)th best sequence when the contents of the (i−1)th path memory and the ith (i=2, 3, . . . , n) path memory of the n candidates of data sequences are coincident.

摘要翻译： 具有LVA检测器的数字磁记录/再现装置，其能够将编码率保持为高达{分数（8/9）}或更大，并且以比现有技术更高的密度进行记录，其中， 为了获得高达（2n-1）个最佳序列（n> 1）的数据序列是以较高似然比的顺序获得的。 可以产生这些数据序列的候选，LVA检测器在其中提供了一个单元，其当第（i）个（i-1）的内容被替换为第（2i-1）个最佳序列时的第i个最佳序列的似然比和路径存储器 -1）路径存储器与第i路径存储器（i = 2,3，...，n）的路径存储器一致，并且第（i-1）个最佳序列与（2i）的最佳序列之间的似然比差的绝对值 -1）的最佳序列小于判定阈值，或将第i个最佳序列的似然比初始化为当第（i-1）个最佳序列的似然比加到内容的第i-1个最佳序列的似然比时的单位， （i-1）路径存储器和n个候选数据序列的第i（i = 2,3，...，n）路径存储器是一致的。

公开(公告)号：US06337889B1

公开(公告)日：2002-01-08

申请号：US09124840

申请日：1998-07-30

申请人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

发明人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

IPC分类号： H04L2706

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009 ,  H04L1/0054

摘要： In a data demodulating method, predetermined input data is based upon a response characteristic of the partial response class 4. The predetermined input data is discrete-filtered to thereby produce filtered asymmetrical data. The filtered asymmetrical data is maximum-likelihood-decoded to thereby produce decoded data that is demodulated. Further, a magnetic recording/reproducing apparatus is arranged by using this data demodulating method.

摘要翻译： 在数据解调方法中，预定输入数据基于部分响应类别4的响应特性。预定输入数据被离散滤波，从而产生滤波后的非对称数据。 滤波的不对称数据是最大似然解码的，从而产生被解调的解码数据。 此外，通过使用该数据解调方法来布置磁记录/再现装置。

公开(公告)号：US07046745B2

公开(公告)日：2006-05-16

申请号：US09986925

申请日：2001-11-13

申请人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

发明人： Seiichi Mita ,  Hideki Sawaguchi ,  Naoya Kobayashi ,  Masaharu Kondo

IPC分类号： H03D1/00 ,  H04B1/10 ,  G11B1/035

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009 ,  H04L1/0054

摘要： In a data demodulating method, predetermined input data is demodulated based upon a response characteristic of the partial response class 4; the demodulated input data is discrete-filtered to thereby produce filtering data; and the filtering data is maximum likelihood-decoded to thereby produce asymmetrical response data. Further, a magnetic recording/reproducing apparatus is arranged by using this data demodulating method.

摘要翻译： 在数据解调方法中，基于部分响应等级4的响应特性来解调预定输入数据; 解调输入数据被离散滤波，从而产生滤波数据; 并且滤波数据被最大似然解码，从而产生非对称响应数据。 此外，通过使用该数据解调方法来布置磁记录/再现装置。

公开(公告)号：US06873665B2

公开(公告)日：2005-03-29

申请号：US09887328

申请日：2001-06-25

申请人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

发明人： Naoya Kobayashi ,  Seiichi Mita ,  Masaharu Kondo ,  Hideki Sawaguchi ,  Takashi Moriyasu

IPC分类号： G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03M13/09 ,  H03M13/23 ,  H03M13/41 ,  H04L25/03 ,  H04L25/08 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/6331 ,  G11B20/10 ,  G11B20/18 ,  H03M13/09 ,  H03M13/41 ,  H03M13/4115 ,  H03M13/4184 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6505 ,  H04L25/03178

摘要： A digital magnetic recording/reproducing apparatus includes an LVA (List Viterbi Algorithm) detector which produces first to nth best sequences (n>1) of a decoded result, and replaces a likelihood ratio and a path memory of the ith best sequence (i=2, 3, . . . , n) with those of the (2i−1)th best sequence when contents of path memories of the (i−1)th and ith best sequences are equal to each other and an absolute value of a difference between likelihood ratios of the (i−1)th and (2i−1)th best sequences is smaller than a decision threshold. Alternatively, the LVA detector initializes a likelihood ratio of the ith best sequence to be a likelihood ratio of the (i−1)th best sequence with a constant difference value added thereto when contents of path memories of the (i−1)th and ith best sequences are equal to each other.

摘要翻译： 一种数字磁记录/重放装置包括一个产生解码结果的第n至第n个最佳序列（n> 1）的LVA（List Viterbi Algorithm）检索器，并将第i个最佳序列（i = 2，3，...，n）与（i-1）和第i个最佳序列的路径存储器的内容彼此相等时的（2i-1）最佳序列的那些，绝对值 （i-1）和（2i-1）最佳序列的似然比之间的差异小于判定阈值。 或者，LVA检测器将第（i-1）个最佳序列的似然比初始化为第（i-1）个最佳序列的似然比，并且当第（i-1）和 最好的序列彼此相等。

公开(公告)号：US07296215B2

公开(公告)日：2007-11-13

申请号：US10922227

申请日：2004-08-18

申请人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

发明人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

IPC分类号： H03M13/03

CPC分类号： H03M13/29 ,  G11B20/10009 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/2703 ,  H03M13/3746 ,  H03M13/45 ,  H03M13/6343 ,  H03M13/6505

摘要： In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

摘要翻译： 在一个实施例中，符号纠错编码器对记录数据执行块交织，并且此后对记录数据执行第一纠错编码。 接下来，符号纠错编码器对整个块执行编码。 再现处理电路输出各位的似然信息。 第一纠错解码器使用似然信息校正记录和再现时产生的随机误差。 由于此时可以通过重复解码对随机误差进行性能改善，所以后校正数据返回到再生处理电路。 在完成这样的重复处理之后，数据被数字化，并通过硬判断进行符号单位的纠错，并将其输出到符号纠错解码器。

公开(公告)号：US20050044468A1

公开(公告)日：2005-02-24

申请号：US10922227

申请日：2004-08-18

申请人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

发明人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/11 ,  H03M13/15 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45 ,  H03M13/00 ,  G11C29/00

CPC分类号： H03M13/29 ,  G11B20/10009 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/2703 ,  H03M13/3746 ,  H03M13/45 ,  H03M13/6343 ,  H03M13/6505

摘要： In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

摘要翻译： 在一个实施例中，符号纠错编码器在记录数据上实现块交错，并且此后对记录数据执行第一纠错编码。 接下来，符号纠错编码器对整个块执行编码。 再现处理电路输出各位的似然信息。 第一纠错解码器使用似然信息校正记录和再现时产生的随机误差。 由于此时可以通过重复解码对随机误差进行性能改善，所以后校正数据返回到再生处理电路。 在完成这样的重复处理之后，数据被数字化，并通过硬判断进行符号单位的纠错，并将其输出到符号纠错解码器。

公开(公告)号：US06725418B2

公开(公告)日：2004-04-20

申请号：US09994062

申请日：2001-11-27

申请人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

发明人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

IPC分类号： H03M1341

CPC分类号： G11B20/10296 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343 ,  H03M13/6502

摘要： A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68. A storing element block output circuit 64 and storing element block output terminals 65(1) to 65(D) are provided in each of the storing element blocks 60(1) to 60(D) so that a path memory circuit output 67 may be outputted through an OR circuit 66.

摘要翻译： 布置最大似然解码电路，通过维特比算法的效果来降低功耗。 在同一时间点垂直定位并用于存储每个状态幸存者路径信息的多个存储元件61a至61h以对应于组合的方式被视为存储元件块60（1）至60（D） 状态）的代码间干扰。 存储元件61a至61h的输出通过路径历史选择电路62a至62h再次应用于包含在相同存储元件块中的相应存储元件的输入。 存储元件块60（1）〜（D）中的每一个在每个处理时间点的接收信号的输入定时通过起始点（指针）63（1）至63（D）从起始点 信号（指针）产生电路68.存储元件块输出电路64和存储元件块输出端子65（1）至65（D）中的每一个都设置在每个存储元件块60（1）至60（D）中，使得 可以通过OR电路66输出路径存储器电路输出67。

公开(公告)号：US06334201B1

公开(公告)日：2001-12-25

申请号：US09093931

申请日：1998-06-09

申请人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

发明人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

IPC分类号： H03M1341

CPC分类号： G11B20/10296 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343 ,  H03M13/6502

摘要： A maximum likelihood decoding circuit is arranged to reduce power consumption through the effect of a Viterbi algorithm. A plurality of storing elements located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks in a manner to correspond to the combination (state) of intracode interferences. The outputs from the storing elements are again applied into the inputs of the corresponding storing elements contained in the same storing element block through path history selecting circuits. Each of the storing blocks is periodically started on the input timing of a receiving signal at each processing time point by starting signals (pointers) outputted from a starting signal (pointer) generated circuit. A storing element block output circuit and storing element block output terminals are provided in each of the storing element blocks so that a path memory circuit output may be outputted through an OR circuit.

摘要翻译： 布置最大似然解码电路以通过维特比算法的效果来降低功耗。 垂直定位在列中并用于在同一时间点存储每个状态幸存者路径信息的多个存储元件被视为对应于帧内干扰的组合（状态）的存储元件块。 来自存储元件的输出通过路径历史选择电路再次应用于包含在相同存储元件块中的相应存储元件的输入。 通过开始从起始信号（指针）产生电路输出的信号（指针），在每个处理时间点，通过接收信号的输入定时周期性地开始每个存储块。 存储元件块输出电路和存储元件块输出端子设置在每个存储元件块中，使得路径存储器电路输出可以通过OR电路输出。

公开(公告)号：US06842875B2

公开(公告)日：2005-01-11

申请号：US10269866

申请日：2002-10-15

申请人： Masaharu Kondo ,  Seiichi Mita

发明人： Masaharu Kondo ,  Seiichi Mita

IPC分类号： G11B20/14 ,  G11B20/18 ,  H03M13/00 ,  H03M13/31

CPC分类号： G11B20/1833 ,  G11B20/1426 ,  G11B2020/1446 ,  H03M13/31

摘要： A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

摘要翻译： 能够减少突发错误产生的信号处理装置，以及使用该信号处理装置的高度可靠的数据记录/再现装置。 该信号处理装置具有在调制码解调器之前提供的简单的错误检测/校正电路，从而校正容易发生在最大似然解码器中的图案的误差。 简单的错误检测/校正电路是使用线性纠错码（例如由循环码形成的纠错码（CRCC））的错误检测/校正电路。 因此，可以减少调制码解调器之后的突发错误的数量。

公开(公告)号：US06493846B1

公开(公告)日：2002-12-10

申请号：US09323703

申请日：1999-06-01

申请人： Masaharu Kondo ,  Seiichi Mita

发明人： Masaharu Kondo ,  Seiichi Mita

IPC分类号： H03M1303

CPC分类号： G11B20/1833 ,  G11B20/1426 ,  G11B2020/1446 ,  H03M13/31

摘要： A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

摘要翻译： 能够减少突发错误产生的信号处理装置，以及使用该信号处理装置的高度可靠的数据记录/再现装置。 该信号处理装置具有在调制码解调器之前提供的简单的错误检测/校正电路，从而校正容易发生在最大似然解码器中的图案的误差。 简单的错误检测/校正电路是使用线性纠错码（例如由循环码形成的纠错码（CRCC））的错误检测/校正电路。 因此，可以减少调制码解调器之后的突发错误的数量。