公开(公告)号：US06725418B2

公开(公告)日：2004-04-20

申请号：US09994062

申请日：2001-11-27

申请人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

发明人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

IPC分类号： H03M1341

CPC分类号： G11B20/10296 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343 ,  H03M13/6502

摘要： A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements 61a to 61h located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks 60(1) to 60(D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements 61a to 61h are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits 62a to 62h. Each of the storing element block 60(1) to 60(D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) 63(1) to 63(D) outputted from a starting signal (pointer) generating circuit 68. A storing element block output circuit 64 and storing element block output terminals 65(1) to 65(D) are provided in each of the storing element blocks 60(1) to 60(D) so that a path memory circuit output 67 may be outputted through an OR circuit 66.

摘要翻译： 布置最大似然解码电路，通过维特比算法的效果来降低功耗。 在同一时间点垂直定位并用于存储每个状态幸存者路径信息的多个存储元件61a至61h以对应于组合的方式被视为存储元件块60（1）至60（D） 状态）的代码间干扰。 存储元件61a至61h的输出通过路径历史选择电路62a至62h再次应用于包含在相同存储元件块中的相应存储元件的输入。 存储元件块60（1）〜（D）中的每一个在每个处理时间点的接收信号的输入定时通过起始点（指针）63（1）至63（D）从起始点 信号（指针）产生电路68.存储元件块输出电路64和存储元件块输出端子65（1）至65（D）中的每一个都设置在每个存储元件块60（1）至60（D）中，使得 可以通过OR电路66输出路径存储器电路输出67。

公开(公告)号：US06334201B1

公开(公告)日：2001-12-25

申请号：US09093931

申请日：1998-06-09

申请人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

发明人： Hideki Sawaguchi ,  Akihiko Hirano ,  Seiichi Mita ,  Terumi Takashi

IPC分类号： H03M1341

CPC分类号： G11B20/10296 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343 ,  H03M13/6502

摘要： A maximum likelihood decoding circuit is arranged to reduce power consumption through the effect of a Viterbi algorithm. A plurality of storing elements located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks in a manner to correspond to the combination (state) of intracode interferences. The outputs from the storing elements are again applied into the inputs of the corresponding storing elements contained in the same storing element block through path history selecting circuits. Each of the storing blocks is periodically started on the input timing of a receiving signal at each processing time point by starting signals (pointers) outputted from a starting signal (pointer) generated circuit. A storing element block output circuit and storing element block output terminals are provided in each of the storing element blocks so that a path memory circuit output may be outputted through an OR circuit.

摘要翻译： 布置最大似然解码电路以通过维特比算法的效果来降低功耗。 垂直定位在列中并用于在同一时间点存储每个状态幸存者路径信息的多个存储元件被视为对应于帧内干扰的组合（状态）的存储元件块。 来自存储元件的输出通过路径历史选择电路再次应用于包含在相同存储元件块中的相应存储元件的输入。 通过开始从起始信号（指针）产生电路输出的信号（指针），在每个处理时间点，通过接收信号的输入定时周期性地开始每个存储块。 存储元件块输出电路和存储元件块输出端子设置在每个存储元件块中，使得路径存储器电路输出可以通过OR电路输出。

公开(公告)号：US20050044468A1

公开(公告)日：2005-02-24

申请号：US10922227

申请日：2004-08-18

申请人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

发明人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/11 ,  H03M13/15 ,  H03M13/27 ,  H03M13/29 ,  H03M13/45 ,  H03M13/00 ,  G11C29/00

CPC分类号： H03M13/29 ,  G11B20/10009 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/2703 ,  H03M13/3746 ,  H03M13/45 ,  H03M13/6343 ,  H03M13/6505

摘要： In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

摘要翻译： 在一个实施例中，符号纠错编码器在记录数据上实现块交错，并且此后对记录数据执行第一纠错编码。 接下来，符号纠错编码器对整个块执行编码。 再现处理电路输出各位的似然信息。 第一纠错解码器使用似然信息校正记录和再现时产生的随机误差。 由于此时可以通过重复解码对随机误差进行性能改善，所以后校正数据返回到再生处理电路。 在完成这样的重复处理之后，数据被数字化，并通过硬判断进行符号单位的纠错，并将其输出到符号纠错解码器。

公开(公告)号：US07296215B2

公开(公告)日：2007-11-13

申请号：US10922227

申请日：2004-08-18

申请人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

发明人： Morishi Izumita ,  Terumi Takashi ,  Hideki Sawaguchi ,  Seiichi Mita

IPC分类号： H03M13/03

CPC分类号： H03M13/29 ,  G11B20/10009 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/2703 ,  H03M13/3746 ,  H03M13/45 ,  H03M13/6343 ,  H03M13/6505

摘要： In one embodiment, a symbol error correction encoder effects block interleaving on recording data and thereafter performs first error correction encoding on the recording data. Next, a symbol error correction encoder performs encoding on the whole block. A reproducing processing circuit outputs likelihood information of respective bits. A first error correction decoder corrects a random error produced upon recording and reproduction, using the likelihood information. Since it is possible to make an improvement in performance with respect to the random error by repetitive decoding at this time, the post-correction data is returned to the reproducing processing circuit. After the completion of such repetitive processing, the data is digitized and subjected to an error correction in symbol unit by a hard determination, and outputted to a symbol error correction decoder.

摘要翻译： 在一个实施例中，符号纠错编码器对记录数据执行块交织，并且此后对记录数据执行第一纠错编码。 接下来，符号纠错编码器对整个块执行编码。 再现处理电路输出各位的似然信息。 第一纠错解码器使用似然信息校正记录和再现时产生的随机误差。 由于此时可以通过重复解码对随机误差进行性能改善，所以后校正数据返回到再生处理电路。 在完成这样的重复处理之后，数据被数字化，并通过硬判断进行符号单位的纠错，并将其输出到符号纠错解码器。

公开(公告)号：US5659309A

公开(公告)日：1997-08-19

申请号：US389773

申请日：1995-02-16

申请人： Terumi Takashi ,  Yasuhide Ouchi ,  Seiichi Mita ,  Akihiko Hirano ,  Naoki Satoh

发明人： Terumi Takashi ,  Yasuhide Ouchi ,  Seiichi Mita ,  Akihiko Hirano ,  Naoki Satoh

IPC分类号： G11B20/18 ,  G11B20/10 ,  H03M13/23 ,  H03M13/41 ,  H03M7/00

CPC分类号： H03M13/6343 ,  G11B20/10009 ,  H03M13/41

摘要： A data recording/reproducing apparatus and method therefor having a Viterbi decoder which stores operation result values of an inputted reproduced signal and the reference value when the peak value of the reproduced signal is updated, compares this value with the reproduced signal in amplitude, updates the stored value when the result satisfies the predetermined condition, detects a change in the polarity of the comparison result, controls the clock counter depending on the status of the peak value updating signal, sets 1 in the shift register at the position indicated by the counter according to the detected polarity inversion signal when the peak value is updated, and accordingly makes the updating and detecting operations independent of operations of addition and subtraction of the current reproduced signal and reference value and operations of addition and subtraction of amplitude comparison.

摘要翻译： 一种数据记录/再现装置和方法，其具有维特比解码器，其在再现信号的峰值被更新时存储输入的再现信号的运算结果值和参考值，将该值与振幅的再现信号进行比较，更新 当结果满足预定条件时，存储值检测比较结果的极性的变化，根据峰值更新信号的状态来控制时钟计数器，根据计数器指示的位置在移位寄存器中设置1 当更新峰值时检测到的极性反转信号，并且因此使得更新和检测操作与当前再现信号的加法和减法操作无关，参考值和幅度比较的相加和减法操作。

公开(公告)号：US06661594B2

公开(公告)日：2003-12-09

申请号：US10277695

申请日：2002-10-23

申请人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

发明人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

IPC分类号： G11B535

CPC分类号： G11B20/10055 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10481

摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

摘要翻译： 一种用于至少包括AGC，PLL，LPF，均衡器电路和检测电路的磁记录/再现装置的信号处理电路，其中通过定义均衡器电路的结构形成系数补偿电路，错误 提供检测电路，其通过接收来自检测电路的输入而工作，并且LSI由多个模拟和数字芯片形成，并且模拟和数字芯片通过电流输出型D / A转换器连接至少至少 AGC和PLL。

公开(公告)号：US6104331A

公开(公告)日：2000-08-15

申请号：US161734

申请日：1998-09-29

申请人： Yoshiteru Ishida ,  Naoki Satoh ,  Terumi Takashi ,  Akihiko Hirano ,  Seiichi Mita

发明人： Yoshiteru Ishida ,  Naoki Satoh ,  Terumi Takashi ,  Akihiko Hirano ,  Seiichi Mita

IPC分类号： G11B5/09 ,  G11B5/012 ,  G11B19/04 ,  G11B20/10 ,  G11B20/24 ,  G11B23/00 ,  H03M1/12 ,  G11B5/02

CPC分类号： G11B19/04 ,  G11B20/10009 ,  G11B20/24 ,  G11B5/012 ,  G11B23/0007 ,  G11B5/09

摘要： A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.

摘要翻译： 再现信号处理电路包括可变增益放大器，从再现头从介质读取的信号被输入到该可变增益放大器; 用于将从可变增益放大器输出的信号转换为数字信号的模拟 - 数字转换器; 以及用于向模数转换器提供操作时钟信号的可变频率振荡器。 再现信号处理方法包括以下步骤：操作用于控制可变增益放大器的第一控制环路; 操作第二控制回路和第三控制回路中的至少一个，控制可变频率振荡器的第二控制回路，控制可变频率振荡器的第三控制回路; 通过模拟滤波器滤波意味着输入到可变增益放大器的读取信号; 操作第一，第二和第三噪声检测操作中的至少一个，所述第一噪声检测操作通过将来自可变增益放大器的输出信号的幅度与预定阈值进行比较来检测噪声的存在或不存在，第二噪声检测 操作在第二控制回路的操作期间检测噪声，第三噪声检测操作在第三控制回路的操作期间检测噪声; 以及根据第一，第二和第三噪声检测操作中的至少一个的结果改变模拟滤波器装置的截止频率的范围，从而控制第一，第二和第三控制回路中的至少一个。

公开(公告)号：US5818655A

公开(公告)日：1998-10-06

申请号：US506635

申请日：1995-07-25

申请人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

发明人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

IPC分类号： G11B5/035 ,  G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10481 ,  G11B5/035 ,  G11B5/09

摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

公开(公告)号：US08117518B2

公开(公告)日：2012-02-14

申请号：US12003270

申请日：2007-12-21

申请人： Terumi Takashi ,  Seiichi Mita ,  Atsushi Saito

发明人： Terumi Takashi ,  Seiichi Mita ,  Atsushi Saito

IPC分类号： G06F11/00

CPC分类号： G11B20/10009 ,  G11B20/00086 ,  G11B20/10055 ,  G11B20/10074 ,  G11B20/10481 ,  G11B20/18 ,  G11B2020/10638 ,  G11B2020/183

摘要： In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly processing data. These processing are achieved that input signal, i.e., raw analog signal read from the recording media is digitized to be stored in a secondary storage such as a memory or a FIFO memory. The apparatus includes a signal processing circuit to repeatedly process the stored digital signal in the secondary storage. When detecting data, operation of the circuit is efficiently controlled by a change over detector parameters, in which characteristics for the detecting performance. Resultantly, data recovery processing speed is increased and reliability of data reproduced is improved.

摘要翻译： 在数据恢复处理中，传统的开销，主要是由旋转记录介质引起的等待时间被去除。 在信号处理或记录和再现装置中，通过重复处理数据来提高数据再现的可靠性。 实现这些处理，即将从记录介质读取的原始模拟信号的输入信号数字化以存储在诸如存储器或FIFO存储器的辅助存储器中。 该装置包括信号处理电路，用于重复处理二次存储器中存储的数字信号。 当检测到数据时，通过改变检测器参数来有效地控制电路的操作，其中检测性能的特性。 从而提高数据恢复处理速度，提高数据再现的可靠性。

公开(公告)号：US06215744B1

公开(公告)日：2001-04-10

申请号：US09504796

申请日：2000-02-15

申请人： Seiichi Mita ,  Terumi Takashi ,  Naoki Satoh

发明人： Seiichi Mita ,  Terumi Takashi ,  Naoki Satoh

IPC分类号： G11B7005

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09

摘要： An information recording/reproducing apparatus includes first and second data demodulators having different data discriminating capabilities. The first data demodulator has a lower data discriminating capability and the second data demodulator has a higher data discriminating capability. When the reliability of reliability information for demodulation data generated by the first data demodulator, the second data demodulator is operated so that demodulation data generated by the first data demodulator is replaced by demodulation data generated by the second data demodulator during a period of time when the reliability of the reliability information is deteriorated.

摘要翻译： 信息记录/再现装置包括具有不同数据鉴别能力的第一和第二数据解调器。 第一数据解调器具有较低的数据鉴别能力，第二数据解调器具有较高的数据识别能力。 当由第一数据解调器产生的解调数据的可靠性信息的可靠性操作时，第二数据解调器被操作，使得由第一数据解调器产生的解调数据被第二数据解调器产生的解调数据替换为在第 可靠性信息的可靠性恶化。