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31.发明申请BLACK PIXEL INSERTING METHOD OF 3D DISPLAY AND CIRCUIT USING THE METHOD 审中-公开使用该方法的3D显示和电路的黑色像素插入方法公开(公告)号：US20160232861A1
公开(公告)日：2016-08-11
申请号：US14378605
申请日：2014-07-02
Inventor： Peng DU
CPC classification number: G09G3/3614 , G09G3/003 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/0861 , G09G2310/0251 , G09G2310/061 , G09G2320/0209 , G09G2320/0252 , G09G2330/021
Abstract: The present invention relates to a black pixel inserting method for 3D display. Multiple data lines for supplying data signals, multiple gate lines for supplying scan signals, and multiple pixels are provided. Each pixel is electrically connected to one data line and one gate line, and the polarity of each pixel is opposite to that of neighboring pixels on the top, bottom, left and right of the pixel. Multiple control transistors for connecting the pixels with different polarities are provided. Multiple control signal terminals electrically connected with the control transistors are provided. When the control signal terminals are applied with a logic low voltage, the control transistors are switched-off, and when the control signal terminals are applied with a logic high voltage, the control transistors are switched-on. In addition, the present invention also provides a circuit using the above method.
Abstract translation: 本发明涉及一种用于3D显示的黑色像素插入方法。 提供用于提供数据信号的多条数据线，用于提供扫描信号的多条栅极线和多个像素。 每个像素电连接到一个数据线和一个栅极线，并且每个像素的极性与像素的顶部，底部，左侧和右侧的相邻像素的极性相反。 提供了用于连接具有不同极性的像素的多个控制晶体管。 提供与控制晶体管电连接的多个控制信号端子。 当控制信号端子施加逻辑低电压时，控制晶体管截止，并且当控制信号端子被施加逻辑高电压时，控制晶体管被接通。 此外，本发明还提供了使用上述方法的电路。
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公开(公告)号：US20150362809A1
公开(公告)日：2015-12-17
申请号：US14416449
申请日：2014-07-04
Inventor： Cong WANG , Ming Hung SHIH , Peng DU
IPC: G02F1/1362 , G02F1/1343 , G02F1/1335 , H01L27/12
CPC classification number: G02F1/136286 , G02F1/136209 , G02F2201/40 , H01L27/124 , H01L27/1255
Abstract: The present disclosure discloses an array substrate, belongs to the technical field of display technology, and solves the technical problem of low aperture ratio of prior liquid crystal display device. The array substrate comprises a plurality of sub pixel units arranged in an array and a plurality of signal lines, wherein one signal line of two adjacent signal lines is arranged in a first side of corresponding sub pixel units, and the other signal line is arranged in a second side of corresponding sub pixel units, said first side and said second side being one of opposite sides of the sub pixel units respectively. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices.
Abstract translation: 本发明公开了一种阵列基板，属于显示技术领域，解决了现有液晶显示装置的低开口率的技术问题。 阵列基板包括排列成阵列的多个子像素单元和多个信号线，其中两个相邻信号线的一个信号线被布置在相应的子像素单元的第一侧，另一个信号线被布置在 相应的子像素单元的第二侧，所述第一侧和所述第二侧分别是子像素单元的相对侧之一。 本公开的阵列基板可以用在液晶电视，液晶显示器，手机，平板电脑等显示装置中。
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公开(公告)号：US20150348483A1
公开(公告)日：2015-12-03
申请号：US14375430
申请日：2014-06-12
Inventor： Peng DU
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G3/3696 , G09G2320/043 , G09G2330/021
Abstract: The present invention provides a driving method of a liquid display panel, comprising: providing a plurality of data lines, a plurality of gate lines (Gate 1-Gate m), and a plurality of pixels (P), and each of the pixels is connected with one data line and one gate line, and the polarity of each of the pixels are opposite to the polarities of adjacent pixels at up, down, left and right; sequentially conducting the gate lines of the pixels which are first polarity corresponding to a driving voltage to complete signal writing of a half frame; sequentially conducting the gate lines of the pixels which are second polarity corresponding to a driving voltage to complete signal writing of the other half frame; the first polarity is opposite to the second polarity, and the m is a multiple of 4. By using the driving method of the liquid display panel, the signal of the data line merely switches the polarity of the driving voltage twice in a period of a frame. The power consumption of the whole panel is reduced. The charging conditions of the pixels are improved and the display quality is enhanced.
Abstract translation: 本发明提供了一种液晶显示面板的驱动方法，包括：提供多条数据线，多条栅极线（Gate 1-Gate m）和多个像素（P），并且每个像素为 与一条数据线和一条栅极线连接，每个像素的极性与上，下，左，右相邻像素的极性相反; 顺序地导通与驱动电压对应的第一极性的像素的栅极线，以完成半帧的信号写入; 顺序地导通与驱动电压对应的第二极性的像素的栅极线，以完成另一半帧的信号写入; 第一极性与第二极性相反，并且m是4的倍数。通过使用液晶显示面板的驱动方法，数据线的信号仅在一段时间内切换驱动电压的极性两次 帧。 整个面板的功耗降低。 改善了像素的充电条件，提高了显示质量。
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公开(公告)号：US20180292692A1
公开(公告)日：2018-10-11
申请号：US14906622
申请日：2016-01-11
Inventor： Peng DU
IPC: G02F1/1368 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/13394 , G02F1/1345 , G02F1/13454 , G02F1/136209 , G02F1/136286 , G02F2001/133388 , H01L27/1244
Abstract: A display panel includes a first substrate and a second substrate. A thin film transistor is disposed on the first substrate. The display panel has a non-display area; the non-display area includes a first metal layer, a frequency signal line formed by a second metal layer and located on the first metal layer, a via (contact hole), and a conducting electrode electrically connecting the first and a second metal layers together. At least a part of the conducting electrode is located in the via. A photo spacer is located in the via, for separating the first substrate and the second substrate. The photo spacer completely covers the conducting electrode. The photo spacer is made of a dielectric material.
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公开(公告)号：US20180130832A1
公开(公告)日：2018-05-10
申请号：US15863993
申请日：2018-01-08
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L27/12 , H01L29/66 , H01L29/786
Abstract: An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.
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Patent Agency Ranking
36.发明申请公开(公告)号：US20180053473A1
公开(公告)日：2018-02-22
申请号：US15318991
申请日：2016-08-19
CPC classification number: G09G3/3406 , G02F1/1333 , G02F2001/136254 , G02F2001/136268 , G09G3/006 , G09G3/3648 , G09G2300/0426 , G09G2300/0439 , G09G2300/0478 , G09G2300/0804 , G09G2310/0264 , G09G2310/0297 , H01L24/02 , H01L27/1214
Abstract: A peripheral design circuit of a liquid crystal display (LCD) panel includes a demultiplexer, a switch test, a driver integrated circuit (driver IC) zone, and a fanout structure. The driver IC zone comprises an upper bonding pad, a lower bonding pad, and a driver IC. The upper bonding pad and the lower bonding pad are arranged opposite. The driver IC is connected to the upper bonding pad and the lower bonding pad. The fanout structure is connected to the lower bonding pad and the demultiplexer. The switch test is arranged between the upper bonding pad and the lower bonding pad. The driver IC covers the switch test. The switch test is connected to the lower bonding pad.
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公开(公告)号：US20170229083A1
公开(公告)日：2017-08-10
申请号：US14905876
申请日：2015-12-23
Inventor： Peng DU
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3696 , G09G2300/0408 , G09G2300/0809 , G09G2310/0286
Abstract: A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels.
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公开(公告)号：US20170222060A1
公开(公告)日：2017-08-03
申请号：US15491941
申请日：2017-04-19
Inventor： Peng DU , Cheng-hung CHEN
IPC: H01L29/786 , H01L21/66 , H01L27/12
CPC classification number: H01L22/34 , H01L22/14 , H01L27/1244 , H01L27/127 , H01L29/66742 , H01L29/78609 , H01L29/78648 , H01L29/78696
Abstract: A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal. The gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.
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公开(公告)号：US20170178578A1
公开(公告)日：2017-06-22
申请号：US14906571
申请日：2015-12-30
Inventor： Peng DU
IPC: G09G3/36 , G02F1/1362 , G02F1/1343 , G02F1/1368
CPC classification number: G09G3/3614 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G09G3/3607 , G09G3/3648 , G09G3/3655 , G09G2300/0439 , G09G2300/0443 , G09G2300/0809 , G09G2310/021 , G09G2320/0209
Abstract: An array substrate is described. The array substrate with a polarity inversion of drive voltage signal in a plurality of data lines comprises a plurality of gate line sets being sequentially arranged, wherein each gate line set comprises two gate lines having an odd gate line and an even gate line respectively; a plurality of data line sets being sequentially arranged and vertically interlaced with the gate line sets, wherein each data line set comprises two data lines having an odd data line and an even data line respectively; wherein a plurality of sub-pixels are sequentially disposed between two adjacent gate line sets, connection positions of a portion of sub-pixels to the odd gate line and the even gate line in one gate line set respectively are changed in a predetermined amount of data line spaced apart.
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公开(公告)号：US20160370624A1
公开(公告)日：2016-12-22
申请号：US14650312
申请日：2015-02-13
IPC: G02F1/1333 , G02F1/1343 , G02F1/1335
CPC classification number: G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/133516 , G02F1/13439 , G02F2001/134318 , G02F2201/121 , G06F3/0412 , G06F3/044 , G06F2203/04103
Abstract: A manufacturing method of a touch display panel is disclosed and has steps of depositing a touch-control metal layer on ail inner side of a color-filler substrate and patterning the touch-control metal layer; depositing a black matrix layer on the inner side of the color-filter substrate and patterning the black matrix layer; depositing a color photoresist layer on the inner side of the color-filter substrate and patterning the color photoresist layer; depositing a common electrode layer on the inner side of the color-filter substrate and patterning the common electrode layer; and performing cell-assembling to assemble the color-filter substrate and an array substrate together.
Abstract translation: 公开了一种触摸显示面板的制造方法，并且具有将触控金属层沉积在彩色填充衬底的内侧并对触摸控制金属层进行图案化的步骤; 在所述滤色器基板的内侧上沉积黑矩阵层并对所述黑矩阵层进行构图; 在彩色滤光片基板的内侧上沉积彩色光致抗蚀剂层，并对彩色光致抗蚀剂层进行构图; 在所述滤色器基板的内侧上沉积公共电极层并对所述公共电极层进行构图; 并且进行电池组装以将滤色器基板和阵列基板组装在一起。
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