公开(公告)号：US20120133215A1

公开(公告)日：2012-05-31

申请号：US13306784

申请日：2011-11-29

申请人： Ming-Iu Lai ,  Shih-Chi Lin

发明人： Ming-Iu Lai ,  Shih-Chi Lin

IPC分类号： H01F38/14 ,  G01R27/28

CPC分类号： H01F38/14

摘要： A positioning method is applied to a movable apparatus and a positioning station. The movable apparatus includes an inducting coil, and the positioning station includes a transmitting coil. The positioning method includes the following steps: transmitting a testing signal via the transmitting coil, inducting the testing signal from the transmitting coil via the inducting coil, measuring an induction value of the inducting coil and driving the movable apparatus to move towards the positioning station according to the induction value.

摘要翻译： 定位方法应用于可动装置和定位台。 可动装置包括感应线圈，定位台包括发射线圈。 定位方法包括以下步骤：通过发射线圈发送测试信号，通过感应线圈感应来自发射线圈的测试信号，测量感应线圈的感应值，并驱动可移动装置向定位台移动 到感应值。

公开(公告)号：US07635651B2

公开(公告)日：2009-12-22

申请号：US11208612

申请日：2005-08-23

申请人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

发明人： Wen-Long Lee ,  Jun Wu ,  Shih-Chi Lin ,  Chyi-Tsong Ni

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31051 ,  H01L21/31053

摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

摘要翻译： 一种平滑电介质层的方法。 首先，提供基板。 接下来，在半导体衬底上形成电介质层。 最后，通过使用硅烷类气体和氮气体气体的等离子体处理使介电层平滑化。

公开(公告)号：US07368383B2

公开(公告)日：2008-05-06

申请号：US11136238

申请日：2005-05-24

申请人： Shih-Chi Lin ,  Francis Wang ,  Wen-Long Lee ,  Sez-An Wu

发明人： Shih-Chi Lin ,  Francis Wang ,  Wen-Long Lee ,  Sez-An Wu

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/02074 ,  Y10S438/906

摘要： A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a cleaning operation that takes place in a wafer scrubber, or subsequent to such an operation. The citric acid treatment removes copper oxides that form on copper surfaces exposed to the environment and prevents hillock formation during subsequent high temperature operations. The copper surface is then annealed and the annealing followed by an NH3 plasma treatment which again removes any copper oxides that may be present. The NH3 plasma operation roughens exposed surfaces improving the adhesion of subsequently-formed films such as a dielectric film preferably formed in-situ with the NH3 plasma treatment. The subsequently-formed film is formed over an oxide-free, hillock-free copper surface.

摘要翻译： 用于处理半导体器件的铜表面的方法在使用CMP（化学机械抛光）或其它方法形成表面之后，使铜表面暴露于柠檬酸溶液。 柠檬酸处理可以在在晶圆洗涤器中进行的清洁操作中或者在这种操作之后进行。 柠檬酸处理除去在暴露于环境的铜表面上形成的铜氧化物，并防止在随后的高温操作期间形成小丘。 然后将铜表面退火，然后进行退火，然后进行NH 3等离子体处理，其再次除去可能存在的任何铜氧化物。 NH 3等离子体操作使暴露的表面粗糙化，改善随后形成的膜的粘附性，例如优选用NH 3等离子体处理原位形成的电介质膜。 随后形成的膜形成在无氧化物的无小丘的铜表面上。

公开(公告)号：US07274353B2

公开(公告)日：2007-09-25

申请号：US10668352

申请日：2003-09-24

申请人： Yen-Chang Chiu ,  Ting-Hao Yeh ,  Yung-Lieh Chien ,  Shih-Chi Lin

发明人： Yen-Chang Chiu ,  Ting-Hao Yeh ,  Yung-Lieh Chien ,  Shih-Chi Lin

IPC分类号： G09G5/00

CPC分类号： G06F3/044 ,  G06F3/04886

摘要： A capacitive touchpad integrated with key and handwriting functions is provided for operation in key, handwriting and mouse modes. Several regions are defined on the panel of the touchpad and have several patterns printed thereon for the operation modes thereby. In the key mode, the key patterns among the printed patterns simulate a keyboard. In the handwriting mode, the handwriting region among the defined regions serves to handwriting input. In the mouse mode, the defined regions provide a cursor moving region and a horizontal and vertical scroll bars for input operations.

摘要翻译： 提供集键盘和手写功能的电容式触控板，用于按键，手写和鼠标模式。 在触摸板的面板上限定几个区域，并且由此为其操作模式印刷了几个图案。 在键模式下，打印图案中的键图案模拟键盘。 在手写模式中，限定区域中的手写区域用于手写输入。 在鼠标模式中，定义的区域提供光标移动区域和用于输入操作的水平和垂直滚动条。

公开(公告)号：US07183199B2

公开(公告)日：2007-02-27

申请号：US10724201

申请日：2003-12-01

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

公开(公告)号：US5950094A

公开(公告)日：1999-09-07

申请号：US252510

申请日：1999-02-18

申请人： Shih-Chi Lin ,  Hui-ju Yu ,  Yen-Ming Chen ,  Hui-Hua Chang

发明人： Shih-Chi Lin ,  Hui-ju Yu ,  Yen-Ming Chen ,  Hui-Hua Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76245 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76283 ,  Y10S148/05 ,  Y10S438/96

摘要： The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions. Ion species can optionally be implanted into the sidewalls of the isolated silicon regions to form lightly doped regions to act as channel stops. A fill oxide layer is deposited over the buried oxide layer and the liner oxide layer. The fill oxide layer and the liner oxide layer are removed down to the level of the top of the isolated silicon regions thereby exposing a fully dielectric isolated silicon.

摘要翻译： 本发明提供了通过在有源区之间形成的沟槽阳极氧化掩埋掺杂硅层来制造全介电隔离硅（FDIS）的方法，以形成多孔硅层; 通过沟槽氧化多孔硅层以形成掩埋氧化物层; 并通过在沟槽中沉积电介质。 该过程开始于在硅衬底中形成掩埋掺杂层，该衬底在导电掩埋掺杂层上限定硅顶层。 图案化硅顶层和掩埋掺杂层以形成延伸到但不穿过掩埋掺杂层的沟槽。 沟槽定义了隔离的硅区域。 掩埋掺杂层被阳极化以形成多孔硅层。 通过氧化将多孔硅层转化为掩埋氧化物层。 氧化步骤还在隔离硅区域的顶部和侧壁上形成衬垫氧化物层。 可以将离子种类任选地注入到隔离的硅区域的侧壁中以形成轻掺杂区域，以充当通道停止。 填埋氧化物层沉积在掩埋氧化物层和衬里氧化物层上。 将填充氧化物层和衬垫氧化物层去除到分离的硅区域的顶部的水平面，从而暴露完全介电的隔离硅。