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    Method for fabricating fully dielectric isolated silicon (FDIS)
    1.
    发明授权
    Method for fabricating fully dielectric isolated silicon (FDIS) 有权
    完全介电隔离硅（FDIS）制造方法

    公开(公告)号：US5950094A

    公开(公告)日：1999-09-07

    申请号：US252510

    申请日：1999-02-18

    申请人： Shih-Chi Lin ,  Hui-ju Yu ,  Yen-Ming Chen ,  Hui-Hua Chang

    发明人： Shih-Chi Lin ,  Hui-ju Yu ,  Yen-Ming Chen ,  Hui-Hua Chang

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76245 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76283 ,  Y10S148/05 ,  Y10S438/96

    摘要： The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions. Ion species can optionally be implanted into the sidewalls of the isolated silicon regions to form lightly doped regions to act as channel stops. A fill oxide layer is deposited over the buried oxide layer and the liner oxide layer. The fill oxide layer and the liner oxide layer are removed down to the level of the top of the isolated silicon regions thereby exposing a fully dielectric isolated silicon.

    摘要翻译： 本发明提供了通过在有源区之间形成的沟槽阳极氧化掩埋掺杂硅层来制造全介电隔离硅（FDIS）的方法，以形成多孔硅层; 通过沟槽氧化多孔硅层以形成掩埋氧化物层; 并通过在沟槽中沉积电介质。 该过程开始于在硅衬底中形成掩埋掺杂层，该衬底在导电掩埋掺杂层上限定硅顶层。 图案化硅顶层和掩埋掺杂层以形成延伸到但不穿过掩埋掺杂层的沟槽。 沟槽定义了隔离的硅区域。 掩埋掺杂层被阳极化以形成多孔硅层。 通过氧化将多孔硅层转化为掩埋氧化物层。 氧化步骤还在隔离硅区域的顶部和侧壁上形成衬垫氧化物层。 可以将离子种类任选地注入到隔离的硅区域的侧壁中以形成轻掺杂区域，以充当通道停止。 填埋氧化物层沉积在掩埋氧化物层和衬里氧化物层上。 将填充氧化物层和衬垫氧化物层去除到分离的硅区域的顶部的水平面，从而暴露完全介电的隔离硅。

    Method of manufacturing self-aligned T-shaped gate through dual damascene
    2.
    发明授权
    Method of manufacturing self-aligned T-shaped gate through dual damascene 有权
    通过双镶嵌制造自对准T形门的方法

    公开(公告)号：US6077733A

    公开(公告)日：2000-06-20

    申请号：US389885

    申请日：1999-09-03

    申请人： Yen-Ming Chen ,  Wei-Jen Liu ,  Shih-Chi Lin ,  Kuo-Chou Liu

    发明人： Yen-Ming Chen ,  Wei-Jen Liu ,  Shih-Chi Lin ,  Kuo-Chou Liu

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L21/338

    CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/42376 ,  H01L29/518

    摘要： A new method is provided to manufacture a T-shaped gate. A layer of insulation is deposited over a semiconductor surface (typically the surface of a substrate), a dual damascene structure containing a via opening and a conducting line trench is created in the layer of insulation. A layer of sacrificial oxide is grown and subsequently removed (preventing initial surface defects and providing protection during subsequent steps of etching). A layer of gate oxide is selectively grown on the bottom of the dual damascene opening. A layer of poly is deposited over the layer of insulation thereby including the dual damascene opening, the poly is planarized down to essentially the top of the dual damascene structure and the insulation is removed from above the surface of the substrate in the regions surrounding the dual damascene structure leaving the dual damascene structure in place.

    摘要翻译： 提供了一种制造T形门的新方法。 绝缘层沉积在半导体表面（通常是衬底的表面）上，在绝缘层中形成包含通孔和导线沟槽的双镶嵌结构。 生长一层牺牲氧化物并随后去除（防止初始表面缺陷并在随后的蚀刻步骤期间提供保护）。 选择性地在双镶嵌开口的底部生长一层栅极氧化物。 一层多晶硅沉积在绝缘层上，从而包括双镶嵌开口，多晶平面化到基本上是双镶嵌结构的顶部，并且在围绕双镶嵌结构的区域中从基板表面上方去除绝缘体 镶嵌结构离开双镶嵌结构就位。

    Method to form polysilicon resistors shielded from hydrogen intrusion
    4.
    发明授权
    Method to form polysilicon resistors shielded from hydrogen intrusion 有权
    形成多晶硅电阻屏蔽氢入侵的方法

    公开(公告)号：US6069063A

    公开(公告)日：2000-05-30

    申请号：US283841

    申请日：1999-04-01

    申请人： Juin-Jie Chang ,  Shih-Chi Lin ,  Yen-Ming Chen ,  Yung-Lung Hsu

    发明人： Juin-Jie Chang ,  Shih-Chi Lin ,  Yen-Ming Chen ,  Yung-Lung Hsu

    IPC分类号： H01L21/02 ,  H01L21/3115 ,  H01L21/314 ,  H01L21/425

    CPC分类号： H01L28/20 ,  H01L21/31155 ,  H01L21/3144

    摘要： A method to form polysilicon resistors shielded from hydrogen intrusion is described. A semiconductor substrate is provided. Field oxide isolation regions are provided overlying the substrate. A polysilicon layer is deposited overlying the field oxide regions and the substrate. The polysilicon layer is etched away where it is not covered by a mask to form a polysilicon resistor. An interlevel dielectric layer is deposited overlying the polysilicon resistor. Nitrogen ions are implanted into the interlevel dielectric layer. The interlevel dielectric layer is annealed to form a silicon oxynitride shield layer in the interlevel dielectric layer. Contact openings are etched through the interlevel dielectric layer to the polysilicon resistor. The contact openings are filled with a metal layer. The metal layer is patterned. The patterned metal layer is covered with a passivation layer wherein the passivation layer contains hydrogen atoms and wherein the silicon oxynitride shield layer prevents hydrogen atoms from penetrating the polysilicon resistor. The integrated circuit is completed.

    摘要翻译： 描述了形成多晶硅电阻器防止氢侵入的方法。 提供半导体衬底。 场氧化物隔离区设置在衬底上。 叠加在场氧化物区域和衬底上的多晶硅层。 多晶硅层被蚀刻掉，其未被掩模覆盖以形成多晶硅电阻器。 沉积层叠介质层覆盖多晶硅电阻器。 将氮离子注入到层间电介质层中。 对层间电介质层进行退火，在层间电介质层中形成氮氧化硅屏蔽层。 接触开口通过层间介质层蚀刻到多晶硅电阻器。 接触开口填充有金属层。 金属层被图案化。 图案化的金属层被钝化层覆盖，其中钝化层含有氢原子，并且其中氮氧化硅屏蔽层防止氢原子穿透多晶硅电阻器。 集成电路完成。

    Method of manufacturing air gap in multilevel interconnection
    5.
    发明授权
    Method of manufacturing air gap in multilevel interconnection 有权
    多层互连制造气隙的方法

    公开(公告)号：US06472719B1

    公开(公告)日：2002-10-29

    申请号：US09624024

    申请日：2000-07-24

    申请人： Shih-Chi Lin ,  Yen-Ming Chen ,  Juin-Jie Chang ,  Kuei-Wu Huang

    发明人： Shih-Chi Lin ,  Yen-Ming Chen ,  Juin-Jie Chang ,  Kuei-Wu Huang

    IPC分类号： H01L2900

    CPC分类号： H01L23/4821 ,  H01L21/764 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the Intra-level dielectric for the metal leads.

    摘要翻译： 一种形成具有空气区域的半导体器件的方法，所述方法包括提供基底，形成金属引线图案，在所述金属引线上沉积氧化物层，在所述氧化物层上形成氮化物层，打开和蚀刻 沟槽到材料的基层，并沉积和平坦化介电层。 一种替代方法教导了在已经沉积在金属引线上的氧化物层上沉积一层SOG，将该层SOG平坦化到金属引线的顶部，沉积一层PECVD氧化物，图案化和蚀刻该 PECVD氧化物层，从而形成位于金属引线之间的开口。 可以去除金属引线之间的SOG，从而产生用于金属引线的内部电介质的气隙。

    Method for manufacturing arch air gap in multilevel interconnection
    6.
    发明授权
    Method for manufacturing arch air gap in multilevel interconnection 有权
    多层互连制造拱空气间隙的方法

    公开(公告)号：US06211057B1

    公开(公告)日：2001-04-03

    申请号：US09389887

    申请日：1999-09-03

    申请人： Shih-Chi Lin ,  Yen-Ming Chen

    发明人： Shih-Chi Lin ,  Yen-Ming Chen

    IPC分类号： H01L214763

    CPC分类号： H01L21/76801 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with the objectives of the invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved. A pattern of metal lines is deposited over an insulating layer. A layer of oxynitride (SiON) is deposited over the pattern of metal lines and the exposed surface of the insulating layer. PECVD oxide is deposited over the layer of oxynitride; the PECVD oxide is removed down to the top surface of the layer of oxynitride overlying the metal pattern. A layer of SOON is deposited over the surface of the polished oxynitride and the polished PECVD oxide. A trench is etched between the conducting line pattern through the layer of SOON and into the PECVD oxide. The profile of this trench is aggressively expanded converting the trench profile from a rectangular profile into an arch-shaped profile. The top region of the arch-shaped profile is closed off by depositing a layer of dielectric over the surface of the layer of SOON.

    摘要翻译： 根据本发明的目的，实现了在半导体电路的相邻导线之间形成气隙的新方法。 金属线的图案沉积在绝缘层上。 在金属线的图案和绝缘层的暴露表面上沉积氮氧化物层（SiON）。 PECVD氧化物沉积在氧氮化物层上; 将PECVD氧化物下移到覆盖金属图案的氮氧化物层的顶表面上。 在抛光的氮氧化物和抛光的PECVD氧化物的表面上沉积一层SOON。 通过SOON层在导线图案之间蚀刻沟槽并进入PECVD氧化物。 该沟槽的轮廓积极地将沟槽轮廓从矩形轮廓转换成拱形轮廓。 通过在SOON层的表面上沉积介电层来封闭拱形轮廓的顶部区域。

    Soft Start Scheme Under Low Voltage Power
    7.
    发明申请
    Soft Start Scheme Under Low Voltage Power 有权
    低压电源下软启动方案

    公开(公告)号：US20130285632A1

    公开(公告)日：2013-10-31

    申请号：US13594896

    申请日：2012-08-27

    申请人： Chih-Ning Chen ,  Yen-Ming Chen

    发明人： Chih-Ning Chen ,  Yen-Ming Chen

    IPC分类号： G05F1/10

    CPC分类号： H02M1/36 ,  H03F3/45192 ,  H03F2203/45674

    摘要： A soft start circuit includes an error amplifier for generating a control signal according to an input voltage, a feedback voltage and a reference voltage, a feedback circuit for generating the feedback voltage according to an output voltage, an internal voltage source for generating a soft start voltage, and a sink circuit including a first transformation module for generating a first transformation current according to the soft start voltage, a second transformation module for generating a second transformation current according to the feedback voltage, a comparison module coupled to the first transformation module and the second transformation module for generating a comparison result according to the first transformation current and the second transformation current, and an output module coupled to the comparison module for generating a sink current according to the comparison result, so as to control the control signal.

    摘要翻译： 软启动电路包括误差放大器，用于根据输入电压，反馈电压和参考电压产生控制信号，用于根据输出电压产生反馈电压的反馈电路，用于产生软启动的内部电压源 电压和宿电路，包括用于根据软启动电压产生第一变换电流的第一变换模块，用于根据反馈电压产生第二变换电流的第二变换模块，耦合到第一变换模块的比较模块和 用于根据第一变换电流和第二变换电流产生比较结果的第二变换模块，以及耦合到比较模块的输出模块，用于根据比较结果产生吸收电流，以便控制控制信号。

    POLY OPENING POLISH PROCESS
    9.
    发明申请
    POLY OPENING POLISH PROCESS 有权

    公开(公告)号：US20120322265A1

    公开(公告)日：2012-12-20

    申请号：US13162776

    申请日：2011-06-17

    申请人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    发明人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC分类号： H01L21/304 ,  H01L21/306

    CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。