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    Integrated circuit and method of fabricating the same
    34.
    发明授权
    Integrated circuit and method of fabricating the same 失效
    集成电路及其制造方法

    公开(公告)号：US5866444A

    公开(公告)日：1999-02-02

    申请号：US617414

    申请日：1996-03-18

    申请人： Shunpei Yamazaki ,  Jun Koyama ,  Toshimitsu Konuma ,  Satoshi Teramoto

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Toshimitsu Konuma ,  Satoshi Teramoto

    IPC分类号： G02F1/1362 ,  H01L21/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/28

    CPC分类号： H01L21/76838 ,  H01L21/4846 ,  H01L23/53219 ,  G02F1/13454 ,  G02F2001/136295 ,  H01L2924/0002

    摘要： An integrated circuit using conductive interconnects made of aluminum or a material consisting chiefly of aluminum. Defects due to hillocks and whiskers are prevented. The integrated circuit is composed of TFTs. Gate interconnects are made of aluminum. Before a metallization film for forming the gate interconnects is patterned, slits are formed in locations where crosstalks and shorts are likely to occur by generation of hillocks and whiskers. The surfaces inside the slits are anodized. The conductive interconnects are formed, using the locations provided with the slits. In this way, during the anodization, unwanted stress is prevented. Furthermore, it is unlikely that a required electric current cannot be supplied for the anodization because of excessive complexity of the interconnection pattern.

    摘要翻译： 使用由铝制成的导电互连或主要由铝构成的材料的集成电路。 防止由于小丘和胡须引起的缺陷。 集成电路由TFT组成。 门互连由铝制成。 在用于形成栅极互连的金属化膜被图案化之前，通过产生小丘和晶须可能发生串扰和短路的位置形成狭缝。 狭缝内的表面被阳极氧化。 使用设置有狭缝的位置形成导电互连。 以这种方式，在阳极氧化期间，防止了不期望的应力。 此外，由于互连图案的过度复杂，不可能为阳极氧化提供所需的电流。