公开(公告)号：US09786610B2

公开(公告)日：2017-10-10

申请号：US14824570

申请日：2015-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hui-Chuan Lu ,  Chun-Hung Lu ,  Po-Yi Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

公开(公告)号：US20140021617A1

公开(公告)日：2014-01-23

申请号：US13677939

申请日：2012-11-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hung Lu ,  Chung-Te Yuan ,  Guang-Hwa Ma

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/73204

Abstract: A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate.

Abstract translation: 提供一种半导体衬底，包括：衬底; 多个导电通孔嵌入基板中; 形成在所述基板上的第一电介质层; 形成在所述第一电介质层上的金属层; 以及形成在所述金属层上的第二电介质层。 因此，当包装基板设置在第二电介质层上时，金属层提供反向应力以平衡由第一和第二电介质层引起的热应力，从而防止半导体衬底翘曲。