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    Interconnection structure for package and fabrication method thereof
    2.
    发明授权
    Interconnection structure for package and fabrication method thereof 有权
    封装的互连结构及其制造方法

    公开(公告)号：US09076796B2

    公开(公告)日：2015-07-07

    申请号：US13894687

    申请日：2013-05-15

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chun-Hung Lin ,  Chun-Hung Lu ,  Guang-Hwa Ma ,  Hsiao-Chun Huang ,  Kuang-Hsin Chen

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/498

    CPC classification number: H01L23/53295 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/49894 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

    Abstract translation: 公开了一种用于封装的互连结构。 互连结构包括在其表面上形成有导电部分的基板主体; 形成在所述基板主体的表面上并且具有用于使所述导电部暴露的通孔的第一光敏介电层; 在通孔中形成的导电通孔; 形成在所述第一光敏介电层上并具有用于使所述导电通孔和所述第一光敏介电层的一部分暴露的开口的第二光敏介电层; 以及形成在第二感光介电层的开口中的导电迹线层，以便通过导电通孔电连接到导电部分，从而简化制造工艺并降低制造成本和时间。

    Package structure and fabrication method thereof
    3.
    发明授权
    Package structure and fabrication method thereof 有权

    公开(公告)号：US10242972B2

    公开(公告)日：2019-03-26

    申请号：US14986149

    申请日：2015-12-31

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Lu-Yi Chen ,  Chang-Lun Lu ,  Shih-Ching Chen ,  Guang-Hwa Ma ,  Cheng-Hsu Hsiao

    IPC: H01L23/58 ,  H01L21/78 ,  H01L25/10 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L25/03

    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.

    SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    半导体基板及其制造方法

    公开(公告)号：US20140021617A1

    公开(公告)日：2014-01-23

    申请号：US13677939

    申请日：2012-11-15

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chun-Hung Lu ,  Chung-Te Yuan ,  Guang-Hwa Ma

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/73204

    Abstract: A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate.

    Abstract translation: 提供一种半导体衬底，包括：衬底; 多个导电通孔嵌入基板中; 形成在所述基板上的第一电介质层; 形成在所述第一电介质层上的金属层; 以及形成在所述金属层上的第二电介质层。 因此，当包装基板设置在第二电介质层上时，金属层提供反向应力以平衡由第一和第二电介质层引起的热应力，从而防止半导体衬底翘曲。

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