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56 条记录 (耗时 0.044 秒)

    Using a timing strobe for synchronization and validation in a digital logic device
    31.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
    32.
    发明授权
    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
    具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化

    公开(公告)号：US06373289B1

    公开(公告)日：2002-04-16

    申请号：US09752895

    申请日：2000-12-26

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： H03K1900

    CPC分类号： H03L7/0812 ,  H03K5/135 ,  H04L25/242

    摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

    摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。

    Floating point multiply accumulator
    36.
    发明授权
    Floating point multiply accumulator 失效

    公开(公告)号：US07080111B2

    公开(公告)日：2006-07-18

    申请号：US09873557

    申请日：2001-06-04

    申请人： Amaresh Pangal ,  Dinesh Somasekhar ,  Shekhar Y. Borkar ,  Sriram R. Vangal

    发明人： Amaresh Pangal ,  Dinesh Somasekhar ,  Shekhar Y. Borkar ,  Sriram R. Vangal

    IPC分类号： G06F7/38

    CPC分类号： G06F7/5443 ,  G06F7/483 ,  G06F7/49936

    摘要： A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

    Memory pass-band signaling
    38.
    发明授权
    Memory pass-band signaling 有权
    存储器通带信令

    公开(公告)号：US06845424B2

    公开(公告)日：2005-01-18

    申请号：US10062034

    申请日：2002-01-31

    申请人： Bryan K. Casper ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  James E. Jaussi

    发明人： Bryan K. Casper ,  Shekhar Y. Borkar ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  James E. Jaussi

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/06

    摘要： A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

    摘要翻译： 存储器系统提供包括分配有频率通带的多个存储器件或存储器器件组。 每个存储器件包括频率转换电路，用于将数据信号上变频和下转换到分配的频率通带。 一些实施例包括通过将多个频率通带分配给每个存储器件或存储器组来同时在存储器件与控制器之间进行双向通信。 存储器系统基板在存储器件占用面积和其它器件占用面积之间提供带通滤波器。

    Method and apparatus for power throttling in a microprocessor using a closed loop feedback system
    39.
    发明授权
    Method and apparatus for power throttling in a microprocessor using a closed loop feedback system 有权

    公开(公告)号：US06330680B1

    公开(公告)日：2001-12-11

    申请号：US09183255

    申请日：1998-10-30

    申请人： Chris S. Browning ,  Shekhar Y. Borkar ,  Gregory E. Dermer

    发明人： Chris S. Browning ,  Shekhar Y. Borkar ,  Gregory E. Dermer

    IPC分类号： G05D2300

    摘要： A method and apparatus for power throttling in a microprocessor. A voltage source supplies voltage to the microprocessor, and a clock source operates the microprocessor at a desired frequency. In one embodiment, a power monitor is configured to measure the short term power consumption of the microprocessor. In another embodiment, a temperature sensor measures the temperature of the microprocessor. Control logic is coupled to the voltage source and the clock source. The control logic receives an indication of the power consumption or temperature, as applicable, and compares it to a predetermined value. In response to the comparison, the control logic varies the supply voltage and the frequency.