公开(公告)号：US20130071977A1

公开(公告)日：2013-03-21

申请号：US13237688

申请日：2011-09-20

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.

摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

公开(公告)号：US20120156837A1

公开(公告)日：2012-06-21

申请号：US13192567

申请日：2011-07-28

申请人： Thilo Scheiper ,  Kerstin Ruttloff ,  Maciej Wiatr ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Kerstin Ruttloff ,  Maciej Wiatr ,  Stefan Flachowsky

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823864

摘要： In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.

摘要翻译： 在复杂的半导体器件中，可以通过使用牺牲隔离元件作为蚀刻掩模而将N沟道晶体管和P沟道晶体管分别完成深漏极和源极区的分布，而不需要任何额外的工艺步骤，并且作为注入掩模 结合用于一种类型晶体管的深漏极和源极区的漏极和源极掺杂物种类。 另一方面，通常的主间隔物可以用于结合另一种晶体管的深漏极和源极区。

公开(公告)号：US08809151B2

公开(公告)日：2014-08-19

申请号：US13232571

申请日：2011-09-14

申请人： Stefan Flachowsky ,  Stephan-Detlef Kronholz ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Stephan-Detlef Kronholz ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.

摘要翻译： 在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性 晶体管在其处理期间。 例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。

公开(公告)号：US20130320450A1

公开(公告)日：2013-12-05

申请号：US13482410

申请日：2012-05-29

申请人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Shiang Yang Ong ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0883 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.

摘要翻译： 提供具有PMOS eSiGe源极/漏极区域的HKMG器件。 实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并在第二HKMG栅极叠层的相对侧形成深的源极/漏极区域 第二个HKMG门栈。

公开(公告)号：US08558290B2

公开(公告)日：2013-10-15

申请号：US13217975

申请日：2011-08-25

申请人： Thilo Scheiper ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L21/82 ,  H01L29/10 ,  H01L23/051 ,  H01L21/76 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.

摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 在一个示例中，该器件包括栅电极和形成在靠近栅电极结构的衬底中的多个源/漏区。 该器件还包括形成在每个源极/漏极区域中的第一金属硅化物区域，其中第一金属硅化物区域具有形成在每个源极/漏极区域中的内部边界和第二金属硅化物区域，其中第二金属硅化物 区域横向位于第一金属硅化物区域的内边界和栅电极结构的边缘之间。

公开(公告)号：US08536033B2

公开(公告)日：2013-09-17

申请号：US13233762

申请日：2011-09-15

申请人： Thilo Scheiper ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L21/425

CPC分类号： H01L27/1203 ,  H01L27/1207

摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

公开(公告)号：US20130178034A1

公开(公告)日：2013-07-11

申请号：US13345922

申请日：2012-01-09

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。

公开(公告)号：US20130049139A1

公开(公告)日：2013-02-28

申请号：US13217792

申请日：2011-08-25

申请人： Steve Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Steve Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78654

摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.

摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。

公开(公告)号：US08329551B2

公开(公告)日：2012-12-11

申请号：US12947460

申请日：2010-11-16

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/66651

摘要： A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant.

摘要翻译： 这里介绍一种半导体器件基板。 半导体器件衬底包括具有第一晶格常数的第一半导体材料层，位于第一半导体材料层中的第二半导体材料的区域和覆盖在第一半导体材料层上的外延生长的第三半导体材料层 第二半导体材料的区域。 第二半导体材料具有与第一晶格常数不同的第二晶格常数。 此外，外延生长的第三半导体材料层表现出覆盖第二半导体材料区域的应力区域。 应力区具有不同于第一晶格常数的第三晶格常数。

公开(公告)号：US08324041B2

公开(公告)日：2012-12-04

申请号：US13023794

申请日：2011-02-09

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L21/8238

CPC分类号： H01L28/20 ,  H01L29/78 ,  H01L29/7843

摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调节电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。