公开(公告)号：US20240063119A1

公开(公告)日：2024-02-22

申请号：US18447701

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Ken-Hsien Hsieh

IPC分类号： H01L23/528 ,  H01L27/085 ,  H01L27/092 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L27/085 ,  H01L27/0924 ,  H01L23/5286 ,  H01L21/76816 ,  H01L23/5226

摘要： A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

公开(公告)号：US20230354572A1

公开(公告)日：2023-11-02

申请号：US18340900

申请日：2023-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-An Lai

IPC分类号： H10B10/00 ,  H01L27/092 ,  G11C5/02 ,  G11C11/412

CPC分类号： H10B10/12 ,  H01L27/092 ,  G11C5/025 ,  G11C11/412

摘要： A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

公开(公告)号：US20230352339A1

公开(公告)日：2023-11-02

申请号：US18344565

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/762 ,  H01L21/74 ,  H01L21/66 ,  H01L21/3115

CPC分类号： H01L21/76243 ,  H01L21/31155 ,  H01L21/743 ,  H01L22/14

摘要： A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

公开(公告)号：US20230275096A1

公开(公告)日：2023-08-31

申请号：US18313971

申请日：2023-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Meng-Hung Shen ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L29/0649 ,  H01L29/7851 ,  H01L29/66795

摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess

公开(公告)号：US11664311B2

公开(公告)日：2023-05-30

申请号：US16746046

申请日：2020-01-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/02 ,  H01L23/528 ,  H01L27/088 ,  G06F30/392 ,  H01L21/027 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/762 ,  H01L23/522 ,  H01L21/3105

CPC分类号： H01L23/5286 ,  G06F30/392 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/31053

摘要： A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.

公开(公告)号：US11637066B2

公开(公告)日：2023-04-25

申请号：US17142016

申请日：2021-01-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Wei Peng ,  Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/768

摘要： An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.

公开(公告)号：US20230053139A1

公开(公告)日：2023-02-16

申请号：US17581365

申请日：2022-01-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Yu Chen ,  Wei-Cheng Tzeng ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  G06F30/392 ,  G06F30/31

摘要： A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

公开(公告)号：US11482473B2

公开(公告)日：2022-10-25

申请号：US16679070

申请日：2019-11-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/48 ,  H01L21/48

摘要： A semiconductor device, including a first metal strip extending in a first direction on a first plane; a second metal strip extending in the first direction on a second plane over the first metal strip; a third metal strip immediate adjacent to the second metal strip and extending in the first direction on the second plane; and a fourth metal strip immediate adjacent to the third metal strip and extending in the first direction on the second plane; wherein the first metal strip and the second metal strip are directed to a first voltage source; wherein a distance between the second metal strip and the third metal strip is greater than a distance between the third metal strip and the fourth metal strip.

公开(公告)号：US20220336458A1

公开(公告)日：2022-10-20

申请号：US17232293

申请日：2021-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Meng-Hung Shen ,  JIann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess

公开(公告)号：US20220284164A1

公开(公告)日：2022-09-08

申请号：US17538028

申请日：2021-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Te-Hsin Chiu ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  H01L23/528

摘要： In some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (PG), are removed after the layout process through a computer-implemented process analogous to solving the N-coloring problem. Through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.