公开(公告)号：US12131998B2

公开(公告)日：2024-10-29

申请号：US18298172

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L23/5286 ,  H01L21/823871 ,  H01L27/092

摘要： A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.

公开(公告)号：US20240321890A1

公开(公告)日：2024-09-26

申请号：US18673632

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L21/764 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

公开(公告)号：US12034076B2

公开(公告)日：2024-07-09

申请号：US17406884

申请日：2021-08-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chih-Liang Chen ,  Lei-Chun Chou ,  Jack Liu ,  Kam-Tou Sio ,  Hui-Ting Yang ,  Wei-Cheng Lin ,  Chun-Hung Liou ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

摘要： A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.

公开(公告)号：US20240222264A1

公开(公告)日：2024-07-04

申请号：US18606944

申请日：2024-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5223 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor device includes a substrate having a first side and a second side; an active region arranged on the first side, and extending along a first lateral direction; a first gate structure arranged on the first side, extending along a second lateral direction perpendicular to the first lateral direction, disposed over the active region, and wrapping a first portion of the active region; a first interconnecting structure arranged on the first side, electrically coupled to the first gate structure, and disposed over the first gate structure; and a second interconnecting structure arranged on the second side, and electrically coupled to one or more portions of the active region. The active region, the first gate structure, the first interconnecting structure, and the second interconnecting structure are collectively configured as a decoupling capacitor.

公开(公告)号：US12021021B2

公开(公告)日：2024-06-25

申请号：US17459697

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC分类号： H01L23/5226 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0207

摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.

公开(公告)号：US11854786B2

公开(公告)日：2023-12-26

申请号：US17344530

申请日：2021-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-An Lai ,  Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Chia-Tien Wu

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226

摘要： An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.

公开(公告)号：US11715636B2

公开(公告)日：2023-08-01

申请号：US17581791

申请日：2022-01-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L23/58

CPC分类号： H01L21/02172 ,  H01L21/0337 ,  H01L23/585

摘要： A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell, the first cell and the second cell are arranged in a first direction; forming a plurality of first metal strips arranged in a second direction and extending in the first direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall extending in the first direction; and fort plurality of second metal strips extending in the second direction on a third plane over the second plane and including a first second metal strip and a second second metal strip separated by the separating wall.

公开(公告)号：US11663389B2

公开(公告)日：2023-05-30

申请号：US17232571

申请日：2021-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Peng ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

摘要： Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

公开(公告)号：US11658119B2

公开(公告)日：2023-05-23

申请号：US17196174

申请日：2021-03-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yi-Bo Liao ,  Kuan-Lun Cheng ,  Wei-Cheng Lin ,  Wei-An Lai ,  Ming Chian Tsai ,  Jiann-Tyng Tzeng ,  Hou-Yu Chen ,  Chun-Yuan Chen ,  Huan-Chieh Su

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/78

摘要： A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

公开(公告)号：US11646314B2

公开(公告)日：2023-05-09

申请号：US17232293

申请日：2021-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Meng-Hung Shen ,  Jiann-Tyng Tzeng

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.