公开(公告)号：US11775727B2

公开(公告)日：2023-10-03

申请号：US16299973

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Hui-Zhong Zhuang ,  Meng-Kai Hsu ,  Pin-Dai Sue ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu ,  Jung-Chou Tsai

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F119/18

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

公开(公告)号：US20220384644A1

公开(公告)日：2022-12-01

申请号：US17814683

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ze-Sian Lu ,  Ting-Wei Chiang ,  Pin-Dai Sue ,  Jung-Hsuan Chen ,  Hui-Wen Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

公开(公告)号：US11469321B2

公开(公告)日：2022-10-11

申请号：US16803261

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ze-Sian Lu ,  Ting-Wei Chiang ,  Pin-Dai Sue ,  Jung-Hsuan Chen ,  Hui-Wen Li

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/24

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

公开(公告)号：US11295055B2

公开(公告)日：2022-04-05

申请号：US17116745

申请日：2020-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Lun Chien ,  Pin-Dai Sue ,  Li-Chun Tien ,  Ting-Wei Chiang ,  Ting Yu Chen

IPC: G06F30/398 ,  G03F1/36 ,  G06F30/392 ,  G06F30/394

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

公开(公告)号：US11030372B2

公开(公告)日：2021-06-08

申请号：US16659351

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Dai Sue ,  Chin-Chou Liu ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.