公开(公告)号：US20220164287A1

公开(公告)日：2022-05-26

申请号：US17666196

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Timothy David ANDERSON ,  Kai CHIRCA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

公开(公告)号：US20220066937A1

公开(公告)日：2022-03-03

申请号：US17498921

申请日：2021-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/084 ,  G06F9/30 ,  G06F12/0895 ,  G06F12/0815 ,  G06F12/128 ,  G06F13/16 ,  G06F12/0817

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

公开(公告)号：US20210390050A1

公开(公告)日：2021-12-16

申请号：US17460410

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

公开(公告)号：US20200371875A1

公开(公告)日：2020-11-26

申请号：US16882382

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Matthew THOMPSON ,  Abhijeet Ashok CHACHAD

IPC: G06F11/10 ,  G06F12/0811 ,  G06F9/52

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.

公开(公告)号：US20240281278A1

公开(公告)日：2024-08-22

申请号：US18654035

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

公开(公告)号：US20230023242A1

公开(公告)日：2023-01-26

申请号：US17958725

申请日：2022-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

公开(公告)号：US20220391283A1

公开(公告)日：2022-12-08

申请号：US17888590

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Matthew THOMPSON ,  Abhijeet Ashok CHACHAD

IPC: G06F11/10 ,  H03M13/15 ,  G06F9/38 ,  G06F12/0879 ,  G06F9/30 ,  G06F9/46 ,  G06F9/448 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F13/16

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.

公开(公告)号：US20220327055A1

公开(公告)日：2022-10-13

申请号：US17847131

申请日：2022-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  Pramod Kumar SWAMI ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/10

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

公开(公告)号：US20220164252A1

公开(公告)日：2022-05-26

申请号：US17670582

申请日：2022-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Son Hung TRAN

IPC: G06F11/10 ,  H03M13/15 ,  G06F9/38 ,  G06F12/0879 ,  G06F9/30 ,  G06F9/46 ,  G06F9/448 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F13/16

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

公开(公告)号：US20210390051A1

公开(公告)日：2021-12-16

申请号：US17460439

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.