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    Transistor device with buffered drain
    32.
    发明授权
    Transistor device with buffered drain 有权

    公开(公告)号：US11876134B2

    公开(公告)日：2024-01-16

    申请号：US17489513

    申请日：2021-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry Litzmann Edwards

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/7824 ,  H01L29/0852 ,  H01L29/1033 ,  H01L29/66681

    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

    Transistors with oxide liner in drift region
    33.
    发明授权
    Transistors with oxide liner in drift region 有权

    公开(公告)号：US11552183B2

    公开(公告)日：2023-01-10

    申请号：US16897382

    申请日：2020-06-10

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Andrew D. Strachan

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266 ,  H01L29/40

    Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE
    37.
    发明申请
    RUGGED LDMOS WITH DRAIN-TIED FIELD PLATE 有权

    公开(公告)号：US20220149186A1

    公开(公告)日：2022-05-12

    申请号：US17092485

    申请日：2020-11-09

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Gang Xue

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/08 ,  H01L21/762

    Abstract: A semiconductor device including a substrate having a semiconductor layer containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A drain-tied field plate on the field relief dielectric, the drain-tied field plate extending from the drain region toward the gate with an electrical connection between the drain-tied field plate and the drain region.

    BCD IC WITH GATE ETCH AND SELF-ALIGNED IMPLANT INTEGRATION
    38.
    发明申请
    BCD IC WITH GATE ETCH AND SELF-ALIGNED IMPLANT INTEGRATION 有权

    公开(公告)号：US20220068649A1

    公开(公告)日：2022-03-03

    申请号：US17411431

    申请日：2021-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Jason R. Heine ,  Pushpa Mahalingam ,  Henry Litzmann Edwards ,  James Robert Todd ,  Alexei Sadovnikov

    IPC: H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

    Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.

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