公开(公告)号：US20140164855A1

公开(公告)日：2014-06-12

申请号：US13709188

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G01R31/318519 ,  G01R31/318555 ,  G11C17/00 ,  G11C29/16 ,  G11C29/36 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中需要不同测试条件的多个存储器被并入到SOC中。 存储测试设置数据的pBIST只读存储器被组织以消除类似的嵌入式存储器的测试设置数据的多个实例。

公开(公告)号：US08598932B2

公开(公告)日：2013-12-03

申请号：US13888050

申请日：2013-05-06

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatasubramanian ,  Anthony Lell ,  Raguram Damodaran

IPC: G06F1/04 ,  H03K21/00

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

Abstract translation: 提供了一个时钟分频器，其配置为将高速输入时钟信号除以奇数，偶数或分数分频比。 例如，输入时钟可以具有1GHz或更高的时钟周期频率。 输入时钟信号被分割以产生输出时钟信号，首先接收表示分频比N的除法因子值F，其中N可以是奇数或偶数整数。 分数指示符表示分数指示符为1时的分频比为N.5，当分数指示符为零时表示分频比为N。 对于分数除数，F被设置为2（N.5）/ 2，并且对于整数分频比，F被设置为N / 2。 当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。 当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。 当分数指示符表示分频比为N.5时，响应于计数指示符的每个断言，合成输出时钟信号的一个周期。 当分数指示符表示分频比是整数时，响应于计数指示符的两个断言，合成输出时钟信号的一个周期。

公开(公告)号：US20130283002A1

公开(公告)日：2013-10-24

申请号：US13918276

申请日：2013-06-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet A. Chachad ,  Ramakrishnan Venkatasubramanian ,  Raguram Damodaran

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

Abstract translation: 在本发明的实施例中，集成电路包括流水线存储器阵列和存储器控制电路。 流水线存储器阵列包含多个存储体。 部分地基于存储体的读取访问时间信息，存储器控制电路被配置为选择在读取延迟期间使用的时钟周期的数量。