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公开(公告)号：US08930783B2
公开(公告)日：2015-01-06
申请号：US13709188
申请日：2012-12-10
Applicant: Texas Instruments Incorporated
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
IPC: G01R31/28 , G11C29/12 , G01R31/3185 , G11C29/36
CPC classification number: G11C29/12 , G01R31/318519 , G01R31/318555 , G11C17/00 , G11C29/16 , G11C29/36 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.
Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中需要不同测试条件的多个存储器被并入到SOC中。 存储测试设置数据的pBIST只读存储器被组织以消除类似的嵌入式存储器的测试设置数据的多个实例。
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2.发明申请pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING IN DIFFERRING VOLTAGE DOMAINS 有权具有多个非同步子串的pBIST架构在差分电压域中运行公开(公告)号：US20140164854A1
公开(公告)日：2014-06-12
申请号：US13709168
申请日：2012-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
IPC: G11C29/12
CPC classification number: G11C29/12 , G11C5/147 , G11C29/12005 , G11C29/16 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.
Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中存储器可能在不同于pBIST的电压域的电压域上工作。 使用多个缓冲器和同步寄存器来避免由桥接各个电压域所需的电压移位器引入的时间延迟引起的元稳定条件。
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3.发明授权pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains 有权具有在不同电压域中工作的多个异步子芯片的pBIST架构公开(公告)号：US09021320B2
公开(公告)日：2015-04-28
申请号：US13709168
申请日：2012-12-10
Applicant: Texas Instruments Incorporated
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
CPC classification number: G11C29/12 , G11C5/147 , G11C29/12005 , G11C29/16 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.
Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中存储器可能在不同于pBIST的电压域的电压域上工作。 使用多个缓冲器和同步寄存器来避免由桥接各个电压域所需的电压移位器引入的时间延迟引起的元稳定条件。
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Patent Agency Ranking
公开(公告)号：US09009550B2
公开(公告)日：2015-04-14
申请号：US13709220
申请日：2012-12-10
Applicant: Texas Instruments Incorporated
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
CPC classification number: G06F11/27 , G11C29/16 , G11C29/32 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.
Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 分布式数据记录器被并入到每个子芯片中，通过串行和压缩的并行数据路径与pBIST进行通信。
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公开(公告)号：US20140164855A1
公开(公告)日：2014-06-12
申请号：US13709188
申请日：2012-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
IPC: G11C29/12
CPC classification number: G11C29/12 , G01R31/318519 , G01R31/318555 , G11C17/00 , G11C29/16 , G11C29/36 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.
Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中需要不同测试条件的多个存储器被并入到SOC中。 存储测试设置数据的pBIST只读存储器被组织以消除类似的嵌入式存储器的测试设置数据的多个实例。
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公开(公告)号：US08977915B2
公开(公告)日：2015-03-10
申请号：US13709247
申请日：2012-12-10
Applicant: Texas Instruments Incorporated
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
CPC classification number: G11C29/16 , G11C11/41 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.
Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。
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公开(公告)号：US20140164856A1
公开(公告)日：2014-06-12
申请号：US13709247
申请日：2012-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
IPC: G11C29/12
CPC classification number: G11C29/16 , G11C11/41 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.
Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。
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公开(公告)号：US20140164844A1
公开(公告)日：2014-06-12
申请号：US13709220
申请日：2012-12-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Raguram Damodaran , Naveen Bhoria , Aman Kokrady
IPC: G06F11/27
CPC classification number: G06F11/27 , G11C29/16 , G11C29/32 , G11C2029/0401
Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.
Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 分布式数据记录器被并入到每个子芯片中，通过串行和压缩的并行数据路径与pBIST进行通信。
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