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    Circuit Layout
    32.
    发明公开
    Circuit Layout 审中-公开

    公开(公告)号：US20230297755A1

    公开(公告)日：2023-09-21

    申请号：US18325501

    申请日：2023-05-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shih-Wei Peng ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

    IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

    CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396

    摘要： Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

    Integrated circuit including super via and method of making
    33.
    发明授权
    Integrated circuit including super via and method of making 有权

    公开(公告)号：US11735517B2

    公开(公告)日：2023-08-22

    申请号：US17590439

    申请日：2022-02-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Kam-Tou Sio ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/528

    摘要： A method including depositing a first dielectric layer over a first conductive line. The method further includes forming a first opening in the first dielectric layer. The method further includes filling the first opening with a first conductive material to define a second conductive line. The method further includes depositing a second dielectric layer over the first dielectric layer. The method further includes forming a second opening in the second dielectric layer. The method further includes filling the second opening with a second conductive material to define a third conductive line. The method further includes forming a supervia opening in the first dielectric layer and the second dielectric layer. The method further includes filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line.

    Integrated circuit, system and method of forming same
    35.
    发明授权
    Integrated circuit, system and method of forming same 有权

    公开(公告)号：US11626369B2

    公开(公告)日：2023-04-11

    申请号：US17237530

    申请日：2021-04-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/8238 ,  H01L23/528 ,  H01L27/092

    摘要： An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

    DECOUPLING CAPACITORS WITH BACK SIDE POWER RAILS
    37.
    发明申请
    DECOUPLING CAPACITORS WITH BACK SIDE POWER RAILS 有权

    公开(公告)号：US20230010409A1

    公开(公告)日：2023-01-12

    申请号：US17370902

    申请日：2021-07-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    摘要： A semiconductor device includes a substrate having a first side and a second side. The semiconductor device on the first side includes: an active region that extends along a first lateral direction and comprises a first sub-region and a second sub-region; a first gate structure that extends along a second lateral direction and is disposed over the active region, with the first and second sub-regions disposed on opposite sides of the first gate structure, wherein the second lateral direction is perpendicular to the first lateral direction; and a first interconnecting structure electrically coupled to the first gate structure. The semiconductor device on the second side includes a second interconnecting structure that is electrically coupled to the first and second sub-regions and configured to provide a power supply. The active region, the first gate structure, the first interconnecting structure, and the second interconnecting structure are collectively configured as a decoupling capacitor.

    Power distribution network
    39.
    发明授权
    Power distribution network 有权

    公开(公告)号：US11444073B2

    公开(公告)日：2022-09-13

    申请号：US17081807

    申请日：2020-10-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

    IPC分类号： H01L27/02 ,  H01L21/84 ,  H01L27/12 ,  H03K3/037 ,  H01L27/118

    摘要： An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    40.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20220238442A1

    公开(公告)日：2022-07-28

    申请号：US17314897

    申请日：2021-05-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/528 ,  H01L27/088 ,  G06F30/392 ,  H01L21/768

    摘要： A semiconductor device includes a first active region, disposed on a first side of a substrate, that extends along a first lateral direction. The semiconductor device includes a second active region, disposed on the first side, that extends along the first lateral direction. The first active region has a first conduction type and the second active region has a second conduction type opposite to the first conduction type. The semiconductor device includes a first interconnect structure, formed on a second side of the substrate opposite to the first side, that includes: a first portion extending along the first lateral direction and vertically disposed below the first active region; and a second portion extending along a second lateral direction. The first latera direction is perpendicular to the first lateral direction.