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公开(公告)号：US07489552B2
公开(公告)日：2009-02-10
申请号：US11501118
申请日：2006-08-09
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C11/34
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
摘要翻译： 在非易失性相变存储器中，利用相变部分的电阻变化来记录信息。 当相变部分产生焦耳热并保持在特定温度时，其进入低电阻状态。 当控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时，通过向控制栅极施加中等电压来限制施加到相变部分的最大电流量，从而避免过热 的相变部。
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公开(公告)号：US20080048166A1
公开(公告)日：2008-02-28
申请号：US11907989
申请日：2007-10-19
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译： 通过高速非易失性相变存储器，提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。 结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。
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公开(公告)号：US20060157680A1
公开(公告)日：2006-07-20
申请号：US11370945
申请日：2006-03-09
IPC分类号： H01L29/04
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译： 通过高速非易失性相变存储器，提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。 结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。
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公开(公告)号：US20090052231A1
公开(公告)日：2009-02-26
申请号：US12162702
申请日：2006-02-02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0078 , G11C2213/79 , H01L27/24
摘要： A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.
摘要翻译： 提供了一种能够高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点处的多个存储单元的存储器阵列的半导体器件中，其中每个存储单元包括信息存储器部分和选择元件，当信息由 用于编程在位线中流动的信息的第一脉冲（复位操作）和与第一脉冲和信息不同的第二脉冲（置位操作）被第三脉冲（读操作）读取，第二脉冲和第三脉冲 脉冲彼此相反。
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公开(公告)号：US20090231913A1
公开(公告)日：2009-09-17
申请号：US12090375
申请日：2005-10-17
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： There is provided a technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.
摘要翻译： 提供了一种能够提高设定操作的速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。
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公开(公告)号：US07796426B2
公开(公告)日：2010-09-14
申请号：US12090375
申请日：2005-10-17
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.
摘要翻译： 一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。
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公开(公告)号：US07859896B2
公开(公告)日：2010-12-28
申请号：US12162702
申请日：2006-02-02
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0078 , G11C2213/79 , H01L27/24
摘要： A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.
摘要翻译： 提供了一种用于高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点的多个存储单元的存储器阵列的半导体器件中，其中每个存储器单元包括信息存储器部分和选择元件，信息由 用于对在位线中流动的信息进行编程的第一脉冲（复位操作），与第一脉冲不同的第二脉冲（设置操作），并且通过第三脉冲（读取操作）读取信息，使得第二脉冲 并且第三脉冲彼此相反。
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公开(公告)号：US20060266992A1
公开(公告)日：2006-11-30
申请号：US11435934
申请日：2006-05-18
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675
摘要： Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer comprising an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.
摘要翻译： 由于硫族化物材料对氧化硅膜的粘附性低，所以存在在相变存储器的制造工序中与膜分离的问题。 此外，由于在相变存储器的复位（非晶化）期间必须将硫属化物材料加热至其熔点以上，所以存在需要非常大的重写电流的问题。 在硫族化物材料层/层间绝缘膜之间和硫族化物材料层/插塞之间插入包含具有粘合剂层和高电阻层（耐热层）两者的极薄绝缘体或半导体的界面层。
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公开(公告)号：US20060203542A1
公开(公告)日：2006-09-14
申请号：US11341385
申请日：2006-01-30
申请人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
发明人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0047 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability is implemented. The memory device includes memory cells, each comprising a first electrode, a second electrode, and an information storage section put between the two electrodes, wherein an operation to feed a first pulse current from the first electrode to the second, and another operation to feed a second pulse current from the second electrode to the first. A segregation of composing elements of the information storage section is caused by applying the first pulse, however, the segregation of elements is resolved by applying the second pulse, and the composition of the element recovers to the original state.
摘要翻译： 实现了具有高可靠性的多次写入操作的半导体非易失性存储器件。 存储器件包括存储单元，每个存储单元包括放置在两个电极之间的第一电极，第二电极和信息存储部分，其中将第一脉冲电流从第一电极馈送到第二电极的操作，以及另一个进给 从第二电极到第一电极的第二脉冲电流。 信息存储部分的组合元件的分离是通过施加第一脉冲引起的，然而，通过应用第二脉冲来解决元件的偏析，并且元件的组成恢复到原始状态。
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公开(公告)号：US07443721B2
公开(公告)日：2008-10-28
申请号：US11341385
申请日：2006-01-30
申请人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
发明人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0047 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability includes memory cells. Each memory cell of the device has a first electrode, a second electrode, and an information storage section between the two electrodes. A segregation of composing elements of the information storage section caused by applying a first current pulse from the first electrode to the second electrode is corrected by applying a second current pulse from the second electrode to the first electrode such that the composition of the storage section recovers to its original state.
摘要翻译： 能够具有高可靠性的多次写入操作的半导体非易失性存储器件包括存储单元。 器件的每个存储单元具有第一电极，第二电极和两个电极之间的信息存储部分。 通过从第二电极向第一电极施加第二电流脉冲来校正由第一电极向第二电极施加第一电流脉冲而引起的信息存储部分的组成元件的分离，使得存储部分的组成恢复 到原来的状态。
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