Far ultraviolet with high luminance emitting high-purity hexagonal boron nitride monocrystalline powder and method of manufacturing the same
    31.
    发明授权
    Far ultraviolet with high luminance emitting high-purity hexagonal boron nitride monocrystalline powder and method of manufacturing the same 有权
    具有高亮度发射高纯度六方氮化硼单晶粉末的远紫外线及其制造方法

    公开(公告)号:US07863554B2

    公开(公告)日:2011-01-04

    申请号:US11988033

    申请日:2006-07-03

    IPC分类号: H01L31/00

    摘要: While high-purity hexagonal boron nitride monocrystal (hBN) obtained by way of a high temperature/high-pressure treatment in the presence of a high-purity solvent has excellent properties in terms of far-UV luminescence characteristics, it has drawbacks including that it can be easily adversely affected by mechanical vibrations and impetus, that monocrystal shows a poor morphological retentiveness and that the luminescence characteristics fluctuate to shift the selected and set wavelength. The present invention can overcome the drawbacks of being easily affected by vibrations and showing a poor morphological retentiveness by grinding down the monocrystal obtained by a solvent/refining process into powder and applying the powder to a light emitting surface. Thus, the present invention provides crystal powder to be used for a far-UV luminescence device showing excellent luminescence characteristics that are stable and do not fluctuate.

    摘要翻译: 虽然在高纯度溶剂存在下通过高温/高压处理获得的高纯度六方氮化硼单晶(hBN)在远紫外发光特性方面具有优异的性能,但其缺点包括: 可以容易地受到机械振动和动力的不利影响,单晶显示出差的形态保持性,并且发光特性波动以移动所选择的和设定的波长。 本发明可以克服通过将通过溶剂/精制过程获得的单晶研磨成粉末并将粉末施加到发光表面上的容易受振动影响并且显示不良形态保持性的缺点。 因此,本发明提供了用于远紫外发光装置的结晶粉末,其表现出稳定且不波动的优异的发光特性。

    Production of a hexagonal boron nitride crystal body capable of emitting out ultraviolet radiation
    33.
    发明授权
    Production of a hexagonal boron nitride crystal body capable of emitting out ultraviolet radiation 有权
    生产能够发出紫外线辐射的六方晶系氮化硼晶体

    公开(公告)号:US07811909B2

    公开(公告)日:2010-10-12

    申请号:US12451641

    申请日:2008-05-22

    IPC分类号: H01L21/00 H01L21/208

    摘要: The invention has for its object to provide a process of synthesizing high-purity hBN crystal bodies on a robust substrate even under normal pressure.The inventive process of producing hexagonal boron nitride crystal bodies is characterized by comprising a preparation step of preparing a mixture of a boron nitride raw material and a metal solvent comprising a transition metal, a contact step of bringing a sapphire substrate in contact with the mixture, a heating step of heating the mixture, and a recrystallization step of recrystallizing at normal pressure a melt obtained in the heating step. It is also characterized by using as the metal solvent a transition metal selected from the group consisting of Fe, Ni, Co, and a combination thereof, and at least one substance selected from the group consisting of Cr, TiN and V without recourse to any sapphire substrate.

    摘要翻译: 本发明的目的是提供即使在常压下也能在坚固的基底上合成高纯度hBN晶体的方法。 制造六方氮化硼晶体的本发明方法的特征在于包括制备氮化硼原料和包含过渡金属的金属溶剂的混合物的制备步骤,使蓝宝石衬底与该混合物接触的接触步骤, 加热混合物的加热步骤和在常压下重结晶在加热步骤中获得的熔体的再结晶步骤。 还特征在于使用选自Fe,Ni,Co及其组合的过渡金属作为金属溶剂,以及选自Cr,TiN和V中的至少一种物质,而不用任何 蓝宝石衬底。

    DIGITAL VIDEO RECEIVER, ECM EXTRACT EQUIPMENT, EMM EXTRACT EQUIPMENT, SCRAMBLE KEY EXTRACT EQUIPMENT, CCI EXTRACT EQUIPMENT, DIGITAL VIDEO RECEIVING SYSTEM, ECM EXTRACT METHOD, EMM EXTRACT METHOD, SCRAMBLE KEY EXTRACT METHOD, CCI EXTRACT METHOD, DIGITAL VIDEO RECEIVING METHOD, AND RECORDING MEDIUM
    35.
    发明申请
    DIGITAL VIDEO RECEIVER, ECM EXTRACT EQUIPMENT, EMM EXTRACT EQUIPMENT, SCRAMBLE KEY EXTRACT EQUIPMENT, CCI EXTRACT EQUIPMENT, DIGITAL VIDEO RECEIVING SYSTEM, ECM EXTRACT METHOD, EMM EXTRACT METHOD, SCRAMBLE KEY EXTRACT METHOD, CCI EXTRACT METHOD, DIGITAL VIDEO RECEIVING METHOD, AND RECORDING MEDIUM 有权
    数字视频接收器,ECM提取设备,EMM提取设备,可提供关键提取设备,CCI提取设备,数字视频接收系统,ECM提取方法,EMM提取方法,可视化提取方法,CCI提取方法,数字视频接收方法和记录 中

    公开(公告)号:US20080095366A1

    公开(公告)日:2008-04-24

    申请号:US11873493

    申请日:2007-10-17

    申请人: Takashi Taniguchi

    发明人: Takashi Taniguchi

    IPC分类号: H04N7/167

    摘要: A decryption process chip has a memory in which a first decryption control unit for decrypting a scramble key by using an ECM and an EMM is downloaded from outside and stored. A stream input unit extracts a packet including the ECM based on first information obtained from the first decryption control unit, and the first decryption control unit extracts the ECM from the packet. An STB control unit extracts only data including the EMM based on second information set up from the first decryption control unit, and the first decryption control unit extracts the EMM from the data. The stream input unit indirectly obtains a scramble key decrypted by the first decryption control unit so as to extract the scramble key and transmit it to a descrambler.

    摘要翻译: 解密处理芯片具有存储器,其中从外部下载用于使用ECM和EMM来解密加密密钥的第一解密控制单元并存储。 流输入单元基于从第一解密控制单元获得的第一信息提取包括ECM的分组,并且第一解密控制单元从分组中提取ECM。 STB控制单元基于从第一解密控制单元设置的第二信息提取包括EMM的数据,并且第一解密控制单元从数据中提取EMM。 流输入单元间接地获得由第一解密控制单元解密的加扰密钥,以提取加密密钥并将其发送到解扰器。

    Method and apparatus for performing floating point arithmetic operation
and rounding the result thereof
    37.
    发明授权
    Method and apparatus for performing floating point arithmetic operation and rounding the result thereof 失效
    用于进行浮点算术运算并舍入其结果的方法和装置

    公开(公告)号:US5633818A

    公开(公告)日:1997-05-27

    申请号:US438142

    申请日:1995-05-08

    申请人: Takashi Taniguchi

    发明人: Takashi Taniguchi

    摘要: An apparatus uses a sticky digit in rounding an interim solution Yr into a final approximate solution Ye for an infinite precise solution Y, determined by a function F according to Y=F(X) with respect to digital data X. The apparatus includes a partial product generator receiving a multiplicand and a multiplier, at least one of which represents an interim solution Yr, for generating a plurality of partial products; a sign inversion generator for generating a sign inversion value, expressed in the same format as the partial products, from at least a lower part of a subtrahend to enable place matching, where the subtrahend represents the digital data X; an adder for adding the partial products and the sign inversion value; a detector which, in response to the addition result, detects whether the subtrahend or a product of the multiplicand and multiplier is greater; and a sticky digit generator for generating the sticky digit in response to the detection result.

    摘要翻译: 一个装置使用一个粘性数字将一个临时解决方案Yr舍入到最终的近似解中,对于无限精确解Y,由相对于数字数据X的Y = F(X)的函数F确定。该装置包括部分 产品生成器接收被乘数和乘数,其中至少一个表示临时解Yr,用于生成多个部分乘积; 符号反转生成器,用于从减数的至少下部生成与所述部分乘积相同格式表示的符号反转值,以使得能够进行位置匹配,其中所述减法表示所述数字数据X; 加法器,用于添加部分乘积和符号反转值; 检测器,响应于相加结果,检测所述被乘数和乘法器的乘法或乘积是否较大; 以及用于响应于检测结果产生粘性数字的粘性数字发生器。

    Method of and apparatus for normalization of a floating point binary
number
    39.
    发明授权
    Method of and apparatus for normalization of a floating point binary number 失效
    浮点二进制数的归一化方法和装置

    公开(公告)号:US5513362A

    公开(公告)日:1996-04-30

    申请号:US049433

    申请日:1993-04-20

    IPC分类号: G06F5/01 G06F7/38

    CPC分类号: G06F5/012

    摘要: A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M. A selecting circuit is adapted to supply, as the exponent e of the result, 0 when CR is equal to 1, and an output (E-LSA) of a subtracting circuit when CR is equal to 0. This enables the denormalize processing of a floating point binary number to be executed at a high speed equivalent to that at which a normalize processing is executed.

    摘要翻译: 作为减法的结果,对尾数M和浮点二进制数的指数E执行后处理,从而获得后处理结果的尾数m和指数e。 因此,将进位1检测电路的减法器的输出(E-1)和输出(尾数消除量LSA的量)输入到最小值选择电路。 当(E-1)小于LSA(即需要进行非规格化处理时),最小值选择电路适于将移位量SH设置为(E-1)和幅度关系判断信号CR至1, 。 当(E-1)不小于LSA(即,当需要归一化处理时),SH被设置为LSA并且CR被设置为0.左移位器适于作为结果的尾数m ,通过执行在尾数M上具有移位量SH的左移处理而获得的值。当CR等于1时,选择电路适于作为结果的指数e提供0,并且输出(E- LSA),当CR等于0时,可以以与执行标准化处理相同的高速度执行浮点二进制数的非规范化处理。

    Small-sized, low power consumption multiplication processing device with
a rounding recoding circuit for performing high speed iterative
multiplication
    40.
    发明授权
    Small-sized, low power consumption multiplication processing device with a rounding recoding circuit for performing high speed iterative multiplication 失效
    具有用于执行高速迭代乘法的舍入式编码电路的小尺寸,低功耗乘法处理装置

    公开(公告)号:US5379244A

    公开(公告)日:1995-01-03

    申请号:US102335

    申请日:1993-09-23

    IPC分类号: G06F7/48 G06F7/52

    CPC分类号: G06F7/4824 G06F7/49947

    摘要: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

    摘要翻译: 一种乘法处理装置,其具有用于将其基数为UPSILON的M位数(M为自然数)分割为连续的N位集(N为等于或小于M的自然数)的记录电路, 并且用于根据Zgi = Cix UPSILON N + Si计算中间和Si和中间进位C1(Zgi是第i集的值(i表示等于或大于预定数的自然数)),并且用于将中间值 对应于第i个对应于对于i的每个值的对应于第(i-1)组的中间进位Ci-1的和Si和用于选择与中间体具有相同格式的一个或多个数字中的一个的选择电路 携带对应于第i组的Ci并将所选择的数字输出到编码电路作为与第(i-1)组对应的中间进位Ci-1。