公开(公告)号：US4751410A

公开(公告)日：1988-06-14

申请号：US746625

申请日：1985-06-19

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L29/94 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944 ,  H03K17/687

CPC classification number: H03K19/0013 ,  H03K19/09429 ,  H03K19/09448

Abstract: A complementary Bi-MIS gate circuit including two CMIS circuits each having a PMIS transistor connected to a high potential source, an NMIS transistor connected to a low potential source, and an impedance element connected between the PMIS and NMIS transistors, and a load driving inverter having a vertically structured pull-up bipolar transistor and a vertically structured pull-down bipolar transistor connected in series. The base terminals of the pull-up and pull-down bipolar transistors are connected to a high voltage level end of the impedance element in one CMIS circuit and to a low voltage level end of the impedance element in the other CMIS circuit respectively. The input signal for the gate circuit is fed to the gate terminals of all the PMIS and NMIS transistors and the output signal of the gate circuit is produced at a connection point between the pull-up and pull-down bipolar transistors. The impedance element in each CMIS circuit works to reduce or remove surge currents which flow through the CMIS circuit when the input signal changes level from low to high or from high to low levels. The Bi-MIS circuit also includes transistors connected in the current paths of the circuit when the circuit is in a high impedance state which cuts off current flow during the high impedance state.

Abstract translation: 一种互补的Bi-MIS门电路，包括两个CMIS电路，每个CMIS电路各自具有连接到高电位源的PMIS晶体管，连接到低电位源的NMIS晶体管和连接在PMIS和NMIS晶体管之间的阻抗元件，以及负载驱动逆变器 具有垂直结构的上拉双极晶体管和串联连接的垂直结构的下拉双极晶体管。 上拉和下拉双极晶体管的基极端子分别连接到一个CMIS电路中的阻抗元件的高电压电平端和另一个CMIS电路中的阻抗元件的低电压电平端。 栅极电路的输入信号被馈送到所有PMIS和NMIS晶体管的栅极端子，并且在上拉和下拉双极晶体管之间的连接点处产生栅极电路的输出信号。 当输入信号从低电平变化到高电平或从高电平变化到低电平时，每个CMIS电路中的阻抗元件用于减少或去除流过CMIS电路的浪涌电流。 当电路处于高阻抗状态时，Bi-MIS电路还包括连接在电路的电流路径中的晶体管，其在高阻抗状态期间截止电流。

公开(公告)号：US4739386A

公开(公告)日：1988-04-19

申请号：US932287

申请日：1986-11-19

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L27/06 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72

CPC classification number: H01L27/0716

Abstract: Switching off time of a bipolar transistor is improved. When the bipolar transistor is driven to a saturation condition, the collector voltage does not go up rapidly when it is switched off again, because once the collector voltage is much less than the base voltage, reverse injection occurs, so the collector voltage can not follow the base voltage until the reverse injected electrons are swept out. In order to avoid saturation, a vertical FET is provided between the base and collector of the bipolar transistor to clamp the base-collector voltage. The channel region of the vertical transistor is formed between the base contact region and collector region of the transistor. Thus, when the transistor is in a non-saturation state, the channel is closed by built in potential, but when the transistor approaches the saturation state, the channel automatically opens to shunt between the base and collector of the bipolar transistor. By replacing a Shottky barrier diode used in prior art circuits for such purposes, with a vertical FET, the device becomes more resignable, and fabrication process is simplified.

Abstract translation: 提高了双极晶体管的关断时间。 当双极晶体管被驱动到饱和状态时，当集电极电压再次关断时，集电极电压不会快速上升，因为一旦集电极电压远低于基极电压，则发生反向注入，因此集电极电压不能跟随 直到反向注入的电子的基极电压被扫除。 为了避免饱和，在双极晶体管的基极和集电极之间提供垂直FET以钳位基极 - 集电极电压。 垂直晶体管的沟道区域形成在晶体管的基极接触区域和集电极区域之间。 因此，当晶体管处于非饱和状态时，通过内置电位闭合通道，但是当晶体管接近饱和状态时，通道自动打开以在双极晶体管的基极和集电极之间分流。 通过用现有技术的电路替代用于这种目的的肖特基势垒二极管，使用垂直FET，器件变得更可辞职，并且制造工艺简化。

公开(公告)号：US4564773A

公开(公告)日：1986-01-14

申请号：US407148

申请日：1982-08-11

Applicant: Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

Inventor： Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/173 ,  H03K19/177 ,  H01L27/00 ,  H03K19/003 ,  H03K19/088

CPC classification number: H03K19/17748 ,  H01L27/11801 ,  H03K19/1735 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  Y10S257/923

Abstract: In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.

Abstract translation: 在具有门阵列结构的半导体器件中，宏单元包括比常规宏单元更多的基本单元，用于预处理逻辑功能，由此在垂直于布线的方向的方向上的端子的密度， 减少。