公开(公告)号：US20060010306A1

公开(公告)日：2006-01-12

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US5124776A

公开(公告)日：1992-06-23

申请号：US492898

申请日：1990-03-13

Applicant: Tetsu Tanizawa ,  Takehito Doi ,  Hideo Tokuda ,  Shigenori Ichinose

Inventor： Tetsu Tanizawa ,  Takehito Doi ,  Hideo Tokuda ,  Shigenori Ichinose

IPC: H01L21/82 ,  H01L27/118

CPC classification number: H01L27/11801

Abstract: A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein. At least a part of the first hierarchical units are arranged in the first direction to form a plurality of second hierarchical units having respective lengths in the first direction wherein the first and second side edges are aligned in the first direction in each of the second hierarchical units. Further, the second hierarchical units are disposed such that there are at least two second hierarchical units having respective positions which are different in the second direction. Furthermore, there is provided a second power feed system extending in the first direction so as to cross the first power feed system for feeding the electric power thereto.

公开(公告)号：US4721995A

公开(公告)日：1988-01-26

申请号：US784439

申请日：1985-10-04

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L21/66 ,  H01L21/768 ,  H01L21/82 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L23/538 ,  H01L23/14 ,  H01L23/54 ,  H01L27/01

CPC classification number: H01L23/4985 ,  H01L23/52 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/14

Abstract: An integrated circuit semiconductor device of very large scale (VLSI) formed in a wafer, namely a wafer IC, is disclosed. In a wafer, a number of circuit blocks are formed in a matrix, being isolated from each other by an intermediate area locating between the circuit blocks. These circuit blocks are connected to interconnecting circuits which are formed on an insulative film in order to complete the wafer IC. The connection is performed by bonding corresponding bonding means, such as pads, disposed on the circuit blocks, repair chips and the interconnecting circuits by a conventional bonding process. With this structure of the wafer IC, the circuit blocks can be accessed easily by a computer aided testing apparatus in advance and the defective circuit blocks can be replaced by good ones, namely repair chips prepared in advance, without any rework of the interconnecting circuits. Bonding pads disposed on the circuit blocks and repair chips are arranged in a predetermined layout pattern for interchangeable bonding, by which the replacement of bad circuit blocks become possible regardless the location of the defective circuit blocks. Two types of the interconnecting film are disclosed for overcoming top surfaces of the repair chips, protruding from the surface of the wafer.

Abstract translation: 公开了一种形成在晶片（即晶片IC）中的非常大规模集成电路半导体器件（VLSI）。 在晶片中，多个电路块以矩阵形成，通过位于电路块之间的中间区彼此隔离。 这些电路块连接到形成在绝缘膜上的互连电路，以便完成晶片IC。 通过通过常规的接合工艺将布置在电路块，修理芯片和互连电路上的相应的接合装置（例如焊盘）接合来进行连接。 利用晶片IC的这种结构，可以预先通过计算机辅助测试装置容易地访问电路块，并且可以用良好的电路块代替缺陷电路块，即预先准备的修理芯片，而不会导致互连电路的返工。 布置在电路块和修复芯片上的接合焊盘以预定的布局图案布置以进行可互换的接合，通过该接合焊盘可以使坏电路块的更换成为可能，而不管电路块的位置如何。 公开了两种类型的互连膜，用于克服从晶片表面突出的修复芯片的顶表面。

公开(公告)号：US4654548A

公开(公告)日：1987-03-31

申请号：US627576

申请日：1984-07-03

Applicant: Tetsu Tanizawa ,  Osam Ohba

Inventor： Tetsu Tanizawa ,  Osam Ohba

IPC: H03K17/04 ,  H01L27/085 ,  H03K19/094 ,  H03K19/017

CPC classification number: H03K19/094 ,  H01L27/085

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit of the present invention is composed from a first stage comprising a complementary MIS-FET, and an output stage comprising a complementary vertical FET. The gate of the V-FET is arranged so as to serve as the drain or source of the MIS-FET. In such an arrangement, the steps of fabricating the IC are reduced and the packing density is increased. By varying the connection of positive and negative voltage sources, the circuit can be operated as an inverting or non-inverting logic circuit.

Abstract translation: 公开了具有大功率处理能力，高开关速度并且仍然具有低功耗的互补逻辑电路。 本发明的电路由包括互补MIS-FET的第一级和包括互补垂直FET的输出级构成。 V-FET的栅极被配置为用作MIS-FET的漏极或源极。 在这种布置中，制造IC的步骤减少，堆积密度增加。 通过改变正负电压源的连接，该电路可以作为反相或非反相逻辑电路运行。

公开(公告)号：US4499484A

公开(公告)日：1985-02-12

申请号：US415795

申请日：1982-09-08

Applicant: Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

Inventor： Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L21/70 ,  H01L21/90 ,  H01L29/44

CPC classification number: H01L23/528 ,  H01L21/82 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/118 ,  H01L2924/14

Abstract: In an integrated circuit manufactured by the master slice method, the feeder line for supplying electric power to a unit-cell array is gradually narrowed in width from the periphery to the middle of the array. As a result, sufficient voltage is supplied to the unit-cells at the middle of the IC and an area of an interconnecting domain for connecting the unit-cells is expanded.

Abstract translation: 在通过主分片方法制造的集成电路中，用于向单元阵列提供电力的馈线从阵列的周边到中间的宽度逐渐变窄。 结果，向集成电路的中间的单位电池供给足够的电压，扩大连接单位电池的互联域的面积。

公开(公告)号：US5556805A

公开(公告)日：1996-09-17

申请号：US372903

申请日：1995-01-17

Applicant: Tetsu Tanizawa ,  Hideo Takuda

Inventor： Tetsu Tanizawa ,  Hideo Takuda

IPC: H01L23/522 ,  H01L21/283

CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A semiconductor device includes a first layer, a first interconnection layer formed on the first layer, at least one dummy pad formed on the first layer in a vicinity of the first interconnection layer, a second layer which is made of an insulator material and is formed on the first layer so as to cover the first interconnection layer and the dummy pad, and a second interconnection layer formed on the second layer and electrically coupled to the first interconnection layer via a via hole in the second layer. The dummy pad is provided in a vicinity of the via hole so that the second layer is approximately flat at least in the vicinity of the via hole, and the dummy pad is electrically isolated from the first and second interconnection layers.

Abstract translation: 半导体器件包括第一层，形成在第一层上的第一互连层，形成在第一互连层附近的第一层上的至少一个虚设焊盘，由绝缘体材料制成的第二层 在第一层上覆盖第一互连层和虚拟焊盘，以及形成在第二层上的第二互连层，并且经由第二层中的通孔电耦合到第一互连层。 所述虚拟焊盘设置在所述通孔的附近，使得所述第二层至少在所述通孔附近大致平坦，并且所述虚拟焊盘与所述第一和第二互连层电隔离。

公开(公告)号：US5384533A

公开(公告)日：1995-01-24

申请号：US59415

申请日：1993-05-11

Applicant: Hideo Tokuda ,  Tetsu Tanizawa

Inventor： Hideo Tokuda ,  Tetsu Tanizawa

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC classification number: G01R31/318569 ,  G06F11/2273

Abstract: A testing method tests functions of a semiconductor integrated circuit which has a plurality of blocks each having a main block circuit part and an output part. The testing method comprises the steps of supplying a control signal to the output part of each of the blocks in a normal mode so that each output part outputs an output data of the main block circuit part of a corresponding one of the blocks, supplying the control signal and a test data to the output part of each of the blocks in a test mode so that each output part outputs the test data which is supplied to the main block circuit part of another block, and comparing the output data and the test data in the output part of each of the blocks in the test mode and outputting a failure detection signal which is indicative of a failure in a corresponding one of the blocks when the compared output data and test data do not match in the one block.

Abstract translation: 测试方法测试具有多个块的半导体集成电路的功能，每个块具有主块电路部分和输出部分。 测试方法包括以正常模式向每个块的输出部分提供控制信号的步骤，使得每个输出部分输出对应的一个块的主块电路部分的输出数据，提供控制 在测试模式中将每个块的输出部分的信号和测试数据发送到测试模块，使得每个输出部分输出提供给另一块的主块电路部分的测试数据，并将输出数据和测试数据进行比较 在测试模式中的每个块的输出部分，并且当比较的输出数据和测试数据在一个块中不匹配时，输出指示相应的一个块中的故障的故障检测信号。

公开(公告)号：US4761572A

公开(公告)日：1988-08-02

申请号：US25709

申请日：1987-03-13

Applicant: Tetsu Tanizawa

Inventor： Tetsu Tanizawa

IPC: H01L21/8234 ,  G11C11/40 ,  H01L27/088 ,  H03K5/00 ,  H03K5/1252 ,  H03K19/003 ,  H03K19/094 ,  H03B1/04

CPC classification number: H03K5/1252 ,  H03K19/00346 ,  H03K19/09429

Abstract: In a semiconductor large scale integrated circuit including a plurality of input terminals, sequential circuits and output buffer circuits, and further comprising a noise cut circuit, the semiconductor large scale integrated circuit comprises: a sense amplifier connected to an input terminal of the output buffer circuit for detecting a change of signal level at the input terminal and for generating an edge detection signal; a pluse generator connected to the sense amplifier for outputting a trigger pulse signal having a predetermined pulse width based on a plurality of the edge detection signals; and at least one tri-state circuit connected between the input terminal and the sequential circuit, and having a control terminal for receiving the trigger pulse signal for obtaining a high impedance state at an output line of the tri-state circuit during a predetermined period based on the trigger pulse signal input from the pulse generator.

Abstract translation: 在包括多个输入端子，顺序电路和输出缓冲电路的半导体大规模集成电路中，还包括噪声切除电路，所述半导体大规模集成电路包括：连接到输出缓冲电路的输入端的读出放大器 用于检测输入端子处的信号电平的变化并产生边沿检测信号; 连接到所述读出放大器的脉冲发生器，用于基于多个边缘检测信号输出具有预定脉冲宽度的触发脉冲信号; 以及连接在输入端子和顺序电路之间的至少一个三态电路，并且具有控制端子，用于接收触发脉冲信号，以在预定时段期间在三态电路的输出线处获得高阻抗状态 对脉冲发生器输入的触发脉冲信号。

公开(公告)号：US4716310A

公开(公告)日：1987-12-29

申请号：US781742

申请日：1985-09-30

Applicant: Tetsu Tanizawa ,  Osam Ohba

Inventor： Tetsu Tanizawa ,  Osam Ohba

IPC: H03K19/08 ,  H03K19/00 ,  H03K19/0944 ,  H03K17/16 ,  H03K5/08 ,  H03K17/60 ,  H03K19/02

CPC classification number: H03K19/0008 ,  H03K19/09448

Abstract: A logical gate circuit includes an emitter-grounded switching transistor and a pull-up circuit connected to a collector of the switching transistor. The switching transistor is cut OFF when an input signal has a high level and is turned ON when the input signal has a low level. A control MIS transistor is connected to a base of the switching transistor and is turned ON and OFF in response to respective low and high levels, of the output terminal of the switching transistor. An input transistor is connected in series with the control MIS transistor and is turned ON and OFF when the input signal is high and low, respectively. Thus, the logical gate circuit allows current to flow only during a transient signal period.

Abstract translation: 逻辑门电路包括发射极接地开关晶体管和连接到开关晶体管的集电极的上拉电路。 当输入信号为高电平时，开关晶体管截止，当输入信号为低电平时，开关晶体管导通。 控制MIS晶体管连接到开关晶体管的基极，并且响应于开关晶体管的输出端子的相应的低电平和高电平而导通和截止。 输入晶体管与控制MIS晶体管串联连接，分别在输入信号为高电平和低电平时导通和截止。 因此，逻辑门电路仅允许电流仅在瞬态信号周期期间流动。

公开(公告)号：US4523106A

公开(公告)日：1985-06-11

申请号：US411269

申请日：1982-08-25

Applicant: Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

Inventor： Tetsu Tanizawa ,  Hitoshi Omichi ,  Yoshiharu Mitono

IPC: H01L21/822 ,  G11C5/02 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/173 ,  H03K19/177 ,  H03K3/26 ,  H01J37/28

CPC classification number: H03K19/17744 ,  G11C5/025 ,  H01L24/06 ,  H01L27/11898 ,  H03K19/1732 ,  H03K19/17796 ,  H01L2224/0603 ,  H01L2924/14 ,  Y10S257/923

Abstract: An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells formed around the inner cell array, a power supply portion having one or more outer power supply lines, and a plurality of inner power supply lines connected to the outer power supply lines and formed on the inner cell array. The ratio of the pitch length of the outer cells to the pitch length of the inner power supply lines or the inner cells is determined by the ratio of two integers. In the integrated circuit device, at least one set of an outer cell, and an inner cell which are arranged in a predetermined positional relation, is formed a plurality of times along a side of the semiconductor chip.

Abstract translation: 一种集成电路装置，例如门阵列或主切片LSI装置，其形成在半导体芯片上，并且包括：内单元阵列，包括多个内单元;外单元阵列，包括围绕内部的多个外单元; 电池阵列，具有一个或多个外部电源线的电源部分和连接到外部电源线并形成在内部单元阵列上的多个内部电源线。 外部单元的音调长度与内部电源线或内部单元的音调长度的比率由两个整数的比率确定。 在集成电路器件中，沿着半导体芯片的一侧多次形成以预定位置关系布置的至少一组外部单元和内部单元。