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公开(公告)号：US07642149B2
公开(公告)日：2010-01-05
申请号：US11907401
申请日：2007-10-11
IPC分类号： H01L21/8238
CPC分类号： H01L29/267 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero junction in combination with the semiconductor base, a gate insulating film so configured as to contact with the hetero junction between the semiconductor base and the hetero semiconductor region, a gate electrode so configured as to contact with the gate insulating film, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor base. The method includes: forming the following in a self-aligning manner, by using a certain mask material: a source contact hole for the source electrode, and the gate electrode.
摘要翻译： 一种半导体器件的制造方法，其特征在于，包括：半导体基底，与半导体基板的半导体材料的带隙不同的半导体材料构成的异质半导体区域，与半导体基板结合形成异质结 基底，被配置为与半导体基底和异质半导体区域之间的异质结接触的栅极绝缘膜，被配置为与栅极绝缘膜接触的栅极电极，连接到异质半导体区域的源极电极，以及 连接到半导体基底的漏电极。 该方法包括：通过使用某种掩模材料：源电极的源极接触孔和栅电极，以自对准的方式形成以下。
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公开(公告)号：US20090267113A1
公开(公告)日：2009-10-29
申请号：US12066145
申请日：2006-08-02
IPC分类号： H01L29/267 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译： 半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。 异质半导体区域具有与半导体基底不同的带隙。 异质半导体区域包括第一异质半导体区域和第二异质半导体区域。 在形成栅极绝缘膜之前形成第一异质半导体区域。 在形成栅极绝缘膜之后形成第二异质半导体区域。
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公开(公告)号：US20090026497A1
公开(公告)日：2009-01-29
申请号：US11988305
申请日：2006-06-26
申请人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译： 公开了一种用于制造半导体器件（20）的方法。 半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A） 所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分 半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。 该方法包括以下顺序操作：i）形成栅极绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。
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34.发明申请METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREFROM 有权制造半导体器件的方法及其制造的半导体器件公开(公告)号：US20080203401A1
公开(公告)日：2008-08-28
申请号：US12033468
申请日：2008-02-19
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.
摘要翻译： 一种制造半导体器件的方法包括：将第一异质半导体层形成为与碳化硅外延层的表面的异质结。 该层由具有与碳化硅外延层的带隙不同的带隙的多晶硅构成。 在第一异质半导体层的表面上形成由具有与多晶硅的蚀刻速率不同的蚀刻速率的材料构成的蚀刻停止层。 形成由多晶硅构成的第二异质半导体层，使得第二异质半导体层与第一异质半导体层和蚀刻停止层的表面接触。 除去蚀刻停止层，将第一异质半导体层热氧化，然后除去热氧化部分。
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公开(公告)号：US20070252172A1
公开(公告)日：2007-11-01
申请号：US11741305
申请日：2007-04-27
IPC分类号： H01L31/00
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/36 , H01L29/4236 , H01L29/45 , H01L29/456 , H01L29/8618
摘要： A semiconductor device, includes: 1) a semiconductor base having a first face; 2) a hetero semiconductor region configured to contact the first face of the semiconductor base and different from the semiconductor base in band gap, the semiconductor base and the hetero semiconductor region defining therebetween a junction part in the hetero semiconductor region, a concentration of an impurity introduced in at least a first certain region including the junction part being less than or equal to a solid solution limit to a semiconductor material included in the hetero semiconductor region; 3) a gate electrode formed, via a gate insulation film, in a certain position adjacent to the junction part; 4) a source electrode configured to be connected to the hetero semiconductor region; and 5) a drain electrode configured to be connected to the semiconductor base.
摘要翻译： 一种半导体器件，包括：1）具有第一面的半导体基底; 2）异质半导体区域，被配置为在带隙中接触半导体基底的第一面并且不同于半导体基底，半导体基底和异质半导体区域在其间限定异质半导体区域中的接合部分，杂质浓度 引入至少包括所述接合部分的第一特定区域小于或等于包含在所述异质半导体区域中的半导体材料的固溶极限; 3）通过栅极绝缘膜在与所述接合部分相邻的特定位置处形成的栅电极; 4）构造成连接到所述异质半导体区域的源电极; 以及5）被配置为连接到所述半导体基底的漏电极。
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公开(公告)号：US20070221955A1
公开(公告)日：2007-09-27
申请号：US11724389
申请日：2007-03-15
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L21/0273 , H01L21/32139 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068
摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
摘要翻译： 形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。 此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。
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公开(公告)号：US20070181886A1
公开(公告)日：2007-08-09
申请号：US11701429
申请日：2007-02-02
IPC分类号： H01L31/0312
CPC分类号： H01L29/267 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.
摘要翻译： 一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域 导电性半导体基板彼此接触，从而形成三重接触点。 第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。
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38.发明授权公开(公告)号：US08067776B2
公开(公告)日：2011-11-29
申请号：US12105318
申请日：2008-04-18
IPC分类号： H01L29/12 , H01L29/76 , H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/66068 , H01L29/513 , H01L29/7828
摘要： Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.
摘要翻译： 本文教导了制造包括半导体衬底和包括具有与半导体衬底的带隙不同的带隙并与半导体衬底的第一表面的一部分接触的半导体材料的半导体区域的半导体器件的制造方法， 设备。 该方法包括在半导体衬底的第一表面的暴露部分和异质半导体材料的暴露表面上沉积第一绝缘膜，并在第一绝缘膜和半导体衬底和异质半导体的相对表面之间形成第二绝缘膜 通过在氧化气氛中进行热处理。
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公开(公告)号：US07989295B2
公开(公告)日：2011-08-02
申请号：US13014190
申请日：2011-01-26
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
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公开(公告)号：US07902555B2
公开(公告)日：2011-03-08
申请号：US12325377
申请日：2008-12-01
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/0847 , H01L29/0623 , H01L29/0642 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.
摘要翻译： 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。
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