公开(公告)号：US11567527B2

公开(公告)日：2023-01-31

申请号：US16519655

申请日：2019-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F1/32 ,  G06F1/14 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3203

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

公开(公告)号：US10935600B2

公开(公告)日：2021-03-02

申请号：US16376697

申请日：2019-04-05

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L29/06

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US20250085730A1

公开(公告)日：2025-03-13

申请号：US18956918

申请日：2024-11-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rinu MATHEW ,  Vineet KHURANA ,  Anand Kumar G ,  Aniruddha PERIYAPATNA NAGENDRA ,  Venkatesh KADLIMATTI ,  Torjus Lyng KALLERUD

IPC: G05F1/46 ,  G01R17/04 ,  H02M1/00 ,  H02M3/156 ,  H02M3/157

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

公开(公告)号：US20250047471A1

公开(公告)日：2025-02-06

申请号：US18362695

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H04L9/06

Abstract: A network-communicating device with a signal input adapted to receive a sensor-derived signal; an analog-to-digital converter (ADC) having an input coupled to the signal input and an output; a data scrambling circuit having an input coupled to the output of the ADC and an output; a watermark insertion circuit having an input coupled to the output of the data scrambling circuit and an output; and a signal output coupled to the output of the watermark insertion circuit.

公开(公告)号：US12181974B2

公开(公告)日：2024-12-31

申请号：US17563398

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Sudhakar Surendran ,  Anand Kumar G

IPC: G06F11/14 ,  G06F11/07 ,  G06F11/22 ,  G06F11/26 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F13/16 ,  G06F13/40 ,  G06F21/10 ,  G06F21/60

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

公开(公告)号：US12181902B2

公开(公告)日：2024-12-31

申请号：US17683217

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rinu Mathew ,  Vineet Khurana ,  Anand Kumar G ,  Aniruddha Periyapatna Nagendra ,  Venkatesh Kadlimatti ,  Torjus Lyng Kallerud

IPC: H02M1/00 ,  G01R17/04 ,  G05F1/46 ,  H02M3/156 ,  H02M3/157

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

公开(公告)号：US12149258B2

公开(公告)日：2024-11-19

申请号：US18437510

申请日：2024-02-09

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G ,  Srinivasa Chakravarthy

IPC: H03M1/12 ,  H03M1/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

公开(公告)号：US20240370341A1

公开(公告)日：2024-11-07

申请号：US18775132

申请日：2024-07-17

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan RAJU ,  Anand Kumar G

IPC: G06F11/16 ,  G06F11/07 ,  G06F11/14 ,  G06F13/20

Abstract: A circuit includes primary register circuitry to receive a first signal to write a first value to the primary register circuitry; secondary register circuitry to receive a second signal to write a second value to the secondary register circuitry; a counter configured to count a set amount of time from when the first signal is received; and a controller coupled to the counter. The controller receives at least one of: a third signal indicating whether the second signal was detected within the set amount of time, and a fourth signal indicating whether the first value is the same as the second value.

公开(公告)号：US20240233787A1

公开(公告)日：2024-07-11

申请号：US18610993

申请日：2024-03-20

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22

CPC classification number: G11C7/109 ,  G11C5/14 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/222

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

公开(公告)号：US11855655B2

公开(公告)日：2023-12-26

申请号：US17710906

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Robin Osa Hoel ,  Anand Kumar G ,  Dhivya Ravichandran ,  Aniruddha Periyapatna Nagendra

IPC: H03M13/09 ,  H03M13/00 ,  G06F13/40

CPC classification number: H03M13/091 ,  G06F13/40 ,  H03M13/611

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.