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55 条记录 (耗时 0.024 秒)

    Full pad coverage boundary scan
    31.
    发明授权
    Full pad coverage boundary scan 有权

    公开(公告)号：US10274538B2

    公开(公告)日：2019-04-30

    申请号：US15722975

    申请日：2017-10-02

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Prakash Narayanan ,  Rajesh Mittal ,  Rajat Mehrotra

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3177

    摘要： An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

    Multiple input signature register analysis for digital circuitry
    32.
    发明授权
    Multiple input signature register analysis for digital circuitry 有权

    公开(公告)号：US10184980B2

    公开(公告)日：2019-01-22

    申请号：US15395307

    申请日：2016-12-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Naman Maheshwari ,  Wilson Pradeep ,  Prakash Narayanan

    IPC分类号： G01R31/317 ,  G01R31/3177 ,  G01R31/3193

    摘要： A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

    AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
    36.
    发明申请
    AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES 审中-公开

    公开(公告)号：US20170125125A1

    公开(公告)日：2017-05-04

    申请号：US15066924

    申请日：2016-03-10

    申请人： Texas Instruments Incorporated

    发明人： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

    IPC分类号： G11C29/12

    CPC分类号： G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/0401 ,  G11C2029/2602

    摘要： A built-in self-test (BIST) parallel memory test architecture for an integrated circuit of the system-on-a-chip (SoC) type. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

    ON-CHIP IR DROP DETECTORS FOR FUNCTIONAL AND TEST MODE SCENARIOS, CIRCUITS, PROCESSES AND SYSTEMS
    38.
    发明申请
    ON-CHIP IR DROP DETECTORS FOR FUNCTIONAL AND TEST MODE SCENARIOS, CIRCUITS, PROCESSES AND SYSTEMS 审中-公开
    用于功能和测试模式场景，电路，过程和系统的片上红外探测器

    公开(公告)号：US20150276824A1

    公开(公告)日：2015-10-01

    申请号：US14735223

    申请日：2015-06-10

    申请人： Texas Instruments Incorporated

    发明人： Prakash Narayanan ,  Sudhir Polarouthu

    IPC分类号： G01R19/257 ,  G01R31/3181

    CPC分类号： G01R19/257 ,  G01R31/3004 ,  G01R31/3181 ,  G01R31/318516

    摘要： An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.

    摘要翻译： 集成电路包括具有电网（20）的功能电路（10），所述电力网（20）具有用于监视的一组电网点（30.i） 以及电子监控电路（100），其具有响应于输入寄存器（155）并且具有输出的可变地可操作的参考电路（150），所述输出具有多个输出并且具有耦合到所述第一输出的输出的第一输入 可变可操作的参考电路（150）和一组第二输入，每个第二输入耦合到所述电网点（30.i）中的相应一个; 和具有分别由所述比较电路（110i）的多个输出端馈送的至少两个寄存器位单元（120）的输出寄存器（120）。 还公开了其他集成电路，以及测试和制造过程。

    Scan chain masking qualification circuit shift register and bit-field decoders
    39.
    发明授权
    Scan chain masking qualification circuit shift register and bit-field decoders 有权
    扫描链屏蔽鉴定电路移位寄存器和位字段解码器

    公开(公告)号：US09091729B2

    公开(公告)日：2015-07-28

    申请号：US14487538

    申请日：2014-09-16

    申请人： Texas Instruments Incorporated

    发明人： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

    IPC分类号： G06F11/00 ,  G01R31/3185

    CPC分类号： G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

    摘要： Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

    摘要翻译： 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。

    Scan chain self-testing of lockstep cores on reset
    40.
    发明授权
    Scan chain self-testing of lockstep cores on reset 有权

    公开(公告)号：US11852683B2

    公开(公告)日：2023-12-26

    申请号：US18155190

    申请日：2023-01-17

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Prakash Narayanan ,  Nikita Naresh

    IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/317

    CPC分类号： G01R31/3177 ,  G01R31/31703 ,  G01R31/31724

    摘要： A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.