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31.发明授权Use of scatterometry/reflectometry to measure thin film delamination during CMP 有权在CMP期间使用散射/反射测量薄膜分层公开(公告)号：US06702648B1
公开(公告)日：2004-03-09
申请号：US10277559
申请日：2002-10-22
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/12
摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
摘要翻译： 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。
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32.发明授权Sensor to predict void free films using various grating structures and characterize fill performance 失效传感器预测使用各种光栅结构的无空隙膜，并表征填充性能公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。
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33.发明授权公开(公告)号：US06673524B2
公开(公告)日：2004-01-06
申请号：US09780275
申请日：2001-02-09
IPC分类号： C08J718
摘要： An exemplary method of forming an attenuating extreme ultraviolet (EUV) phase-shifting mask is described. This method can include providing a multi-layer mirror over an integrated circuit substrate or a mask blank, providing a buffer layer over the multi-layer mirror, providing a dual element material layer over the buffer layer, and selectively growing features on the integrated circuit substrate or mask blank using a photon assisted chemical vapor deposition (CVD) process when depositing the dual element layer.
摘要翻译： 描述形成衰减极紫外（EUV）移相掩模的示例性方法。 该方法可以包括在集成电路衬底或掩模板上提供多层反射镜，在多层反射镜上提供缓冲层，在缓冲层上提供双重元件材料层，以及在集成电路上选择性地增长特征 衬底或掩模坯料，当沉积双重元件层时，使用光子辅助化学气相沉积（CVD）工艺。
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34.发明授权Defect detection in pellicized reticles via exposure at short wavelengths 有权通过在短波长下的曝光在斑点状掩模版中的缺陷检测公开(公告)号：US06665065B1
公开(公告)日：2003-12-16
申请号：US09829195
申请日：2001-04-09
申请人： Khoi A. Phan , Bhanwar Singh , Wolfram Porsche
发明人： Khoi A. Phan , Bhanwar Singh , Wolfram Porsche
IPC分类号： G01N2100
CPC分类号： G01N21/95692
摘要： A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.
摘要翻译： 提供了用于检测掩模或掩模版中的潜在缺陷的系统和方法，该缺陷可以随曝光波长的辐射而变化。 作为示例，检查掩模或掩模版，暴露于指定波长的辐射，然后再检查。 暴露前后的检查结果之间的相关性提供暴露相关缺陷的指示，其可以包括由暴露引起的缺陷生长和/或形成缺陷。 为了进一步说明，掩模或掩模版的检查和曝光的组合可以相对于薄膜掩模或掩模版实现，以便检测与使用掩模或掩模版的防护薄膜相关的附加缺陷。
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35.发明授权公开(公告)号：US06633392B1
公开(公告)日：2003-10-14
申请号：US10052142
申请日：2002-01-17
IPC分类号： G01B1128
CPC分类号： H01L21/67253 , G01N23/20 , H01L22/26
摘要： One aspect of the present invention relates to a method to facilitate formation of an oxide portion of an anti-reflective layer on a substrate. The method involves the steps of forming an oxidized portion of an anti-reflective coating over an anti-reflective layer disposed on the substrate; reflecting a beam of x-ray radiation at the oxidized portion; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the oxidized portion based on the measurement signal while the oxidized portion is being formed at the substrate.
摘要翻译： 本发明的一个方面涉及一种便于在基底上形成抗反射层的氧化物部分的方法。 该方法包括以下步骤：在设置在基底上的抗反射层上形成抗反射涂层的氧化部分; 在氧化部分反射一束x射线辐射; 基于所述光束的反射部分生成测量信号; 并且在氧化部分形成在基板上的同时基于测量信号确定氧化部分的厚度。
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公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译： 提供了一种用于调节开发过程的时间和温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的显影进展。 该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。 该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。 处理器选择性地控制加热装置，以调节晶片各部分的温度。
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37.发明授权Reducing resist residue defects in open area on patterned wafer using trim mask 有权使用修剪掩模减少图案化晶片上的开放区域中的抗蚀剂残留缺陷公开(公告)号：US06613500B1
公开(公告)日：2003-09-02
申请号：US09824079
申请日：2001-04-02
IPC分类号： G03F700
CPC分类号： G03F7/70425 , G03F7/2022 , G03F7/203 , G03F7/70466
摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.
摘要翻译： 本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。 该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。
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公开(公告)号：US06594024B1
公开(公告)日：2003-07-15
申请号：US09886863
申请日：2001-06-21
IPC分类号： G01B1128
CPC分类号： B24B37/005 , B24B49/12 , G01N21/47 , G01N21/9501 , H01L21/30625
摘要： One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.
摘要翻译： 本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统，以便确定包括晶片的CMP工艺端点，其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库，以确定晶片的状态。 另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法，其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。
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39.发明授权System and method for measuring dimensions of a feature having a re-entrant profile 有权用于测量具有入口轮廓的特征的尺寸的系统和方法公开(公告)号：US06559446B1
公开(公告)日：2003-05-06
申请号：US09670775
申请日：2000-09-27
申请人： Bryan K. Choo , Bhanwar Singh
发明人： Bryan K. Choo , Bhanwar Singh
IPC分类号： G01N23225
CPC分类号： G01N23/225
摘要： A system and method are disclosed for measuring and/or imaging a feature having a re-entrant cross-sectional profile. Beams are emitted onto the feature and substrate at different angles during corresponding measurement intervals. An feature data set of the feature is characterized for each measurement interval. The data associated with each measurement interval are aggregated to provide a cross-sectional representation of the having dimensions proportional to the feature. As a result, a more accurate feature profile may be determined, including a cross-sectional dimension of the re-entrant feature at the juncture between the feature and substrate.
摘要翻译： 公开了一种用于测量和/或成像具有重入横截面轮廓的特征的系统和方法。 光束在相应的测量间隔内以不同的角度发射到特征和基底上。 特征的特征数据集的特征在于每个测量间隔。 与每个测量间隔相关联的数据被聚合以提供具有与特征成比例的尺寸的横截面表示。 结果，可以确定更准确的特征轮廓，包括在特征和基底之间的交界处的入侵特征的横截面尺寸。
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公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译： 本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。 本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。 与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。 散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。 也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。
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