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31.发明授权Method and apparatus for controlling timing of execution of saving and restoring operations in a processor system 失效用于控制处理器系统中的保存和恢复操作的执行时序的方法和装置
公开(公告)号：US5642499A
公开(公告)日：1997-06-24
申请号：US223834
申请日：1994-04-06
申请人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
发明人： Mamoru Ohba , Shigeki Morinaga , Mitsuru Watabe , Hiroyuki Kida
CPC分类号： G06F9/461 , G06F9/30025 , G06F9/3861 , G06F9/3885
摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.
摘要翻译： 在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。 响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令 的当前命令，如果当前命令是一个短命令。 基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。
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公开(公告)号：US5351027A
公开(公告)日：1994-09-27
申请号：US852663
申请日：1992-03-17
CPC分类号： G01R33/09
摘要： A magnetic sensor has a elongate sensor region formed by an elongate magneto-resistive element and an overlapping elongate conductive element. The ends of the magneto-resistive element and the conductive element are connected to terminals which are arranged in an array which is spaced in a predetermined direction from the elongate sensor region. The array may be at one side or one end of the elongate sensor region, and the terminals may have a linear arrangement within the array. The two terminals connected to the magneto-resistive element are preferably adjacent, and preferably the terminals connected to the ends of the magneto-resistive element and the conductive element closer to the array are also adjacent. A common terminal may be provided. Two such sensors may form a sensor array which is particularly suitable for use in a position sensor in e.g. a torque sensor of a power steering system.
摘要翻译： 磁传感器具有由细长磁阻元件和重叠的细长导电元件形成的细长传感器区域。 磁阻元件和导电元件的端部连接到以与从细长传感器区域预定方向隔开的阵列布置的端子。 阵列可以在细长传感器区域的一侧或一端，并且端子可以在阵列内具有线性排列。 连接到磁阻元件的两个端子优选地相邻，并且优选地，连接到磁阻元件的端部和更靠近阵列的导电元件的端子也相邻。 可以提供公共终端。 两个这样的传感器可以形成特别适合用于例如位置传感器的传感器阵列。 动力转向系统的转矩传感器。
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公开(公告)号：US5349351A
公开(公告)日：1994-09-20
申请号：US940332
申请日：1992-09-03
申请人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
发明人： Sanshiro Obara , Mitsuru Watabe , Rika Minami , Shigeki Morinaga
CPC分类号： H03M1/1225
摘要： An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.
摘要翻译： 模拟数字转换装置被设计成当同时指示将特殊模拟信号转换为数字信号的操作和将另一个模拟信号转换为数字信号的操作时，优先考虑特殊模拟信号的转换操作 模拟数字转换装置包括具有主信道和子信道的模拟多路复用器，样本保持器，AD转换器，具有多个存储区域的转换结果寄存器，以及用于控制驱动器的AD控制电路 各个组件根据CPU的指令。 当输入到通道的模拟信号按顺序转换为数字信号时，通过AD转换将模拟信号输入到主通道的模拟信号的AD转换优先给输入到子通道。
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公开(公告)号：US5293558A
公开(公告)日：1994-03-08
申请号：US536565
申请日：1990-07-03
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： PCT No.PCT / JP89 / 01134 Sec。 371日期1990年7月3日 102（e）日期1990年7月3日PCT提交1989年11月2日PCT公布。 出版物WO90 / 05335 日期1990年5月17日。一种乘法，除法和平方根提取装置，其通过使用迭代近似来计算加法，除法和平方根提取函数的解，具有连接到a的规定位宽的乘法器，加法器 - 减法器和移位器 总线。 通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。 通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。
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35.发明授权System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus 失效在多协处理器装置中使用微处理器地址线进行协处理器选择的系统
公开(公告)号：US5125095A
公开(公告)日：1992-06-23
申请号：US678906
申请日：1991-03-28
申请人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.
摘要翻译： 微计算机系统具有微处理器和多个独立的协处理器，用于根据从微处理器发送的指令数据执行各个指令。 地址总线和数据总线将协处理器与微处理器互连。 微处理器通过数据总线向协处理器发送指令数据，同时通过地址总线向协处理器发送协处理器指定数据。 由指定数据指定的协处理器读取并对指令数据进行响应，而系统内的其他协处理器忽略指令数据。
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公开(公告)号：US4621224A
公开(公告)日：1986-11-04
申请号：US721959
申请日：1985-04-11
CPC分类号： G01P3/489
摘要： A position/speed detection method and apparatus employing an encoder mounted on the rotary shaft of a motor in order to control the position and speed, wherein the coarse position and fine position are simultaneously detected by an encoder pulse and an encoder original signal, respectively and the detected results are combined to detect the position and speed of the motor with high precision.
摘要翻译： 一种位置/速度检测方法和装置，其使用安装在电机的旋转轴上的编码器来控制位置和速度，其中粗略位置和精细位置分别由编码器脉冲和编码器原始信号同时检测， 结合检测结果，高精度地检测电机的位置和速度。
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公开(公告)号：USRE32163E
公开(公告)日：1986-05-27
申请号：US511590
申请日：1983-07-07
CPC分类号： F02P5/1504 , F02D41/26 , F02P15/006 , Y02T10/46
摘要： An electronic control apparatus includes a digital processor which receives data from sensors indicating conditions of the engine and supplies output control data for operating various actuators which control the engine operation. The interfacing of data between the sensors, the digital processor and the actuators is effected through a set of registers and a controlled incrementing device. The set of registers includes a plurality of reference registers which store engine control data supplied from the digital processor. Another set of registers store respective sets of codes the values of which are sequentially and selectively incremented in accordance with a prescribed timing signal pattern during the rotation of the engine crankshaft. The data in these respective registers are compared with one another and upon the contents of a register, the contents of which are incremented by the timing signal pattern reaching the value stored in the reference register the data contained in which is supplied from the digital processor, an output is supplied to operate a respective engine actuator. Since the data supplied by the digital processor may vary at any time depending upon operating conditions, which are supplied by the digital processor, are not fixed but are subject to variation. If, at the time the digital processor is modifying or changing, namely updating, the data contained in a reference register, the value in a corresponding one of the second set of registers becomes equal to the old data with which it has been compared, no output signal is permitted to be supplied to an engine actuator until after the new data supplied by the digital processor has been input to the appropriate reference register. This preventing or inhibiting action enables the system to control the engine actuators in an extremely accurate manner, as the reference data upon which actuator control signals are ultimately based is always permitted to be dynamically updated so that the engine is always controlled on the basis of current engine conditions.
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公开(公告)号：USRE32140E
公开(公告)日：1986-05-06
申请号：US509769
申请日：1983-06-30
CPC分类号： F02D41/0077 , F02D41/28 , F02P5/1502 , F02D2041/2027 , F02M26/53 , Y02T10/46 , Y02T10/47
摘要： An electronic engine control apparatus in which the timing of the ignition and the fuel injection are calculated from a negative pressure in the intake manifold of the engine or the flow rate of suction air and the rotational speed of the engine. A reference register group is constituted of registers for storing the result of the calculation while an instantaneous register group is made up of registers for storing the instantaneous states of actuators. One of the registers of the reference register group and one of the registers of the instantaneous register group are selected according to a stage timing signal so that the contents of the two registers selected are compared with each other.
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公开(公告)号：US4277829A
公开(公告)日：1981-07-07
申请号：US952276
申请日：1978-10-18
IPC分类号： F02D41/34 , F02D21/08 , F02D41/26 , F02D45/00 , F02P5/15 , F02P15/00 , G05B15/02 , F02D5/00 , G06F11/00
CPC分类号： F02P5/1504 , F02D41/26 , F02P15/006 , Y02T10/46
摘要： An electronic control apparatus includes a digital processor which receives data from sensors indicating conditions of the engine and supplies output control data for operating various actuators which control the engine operation. The interfacing of data between the sensors, the digital processor and the actuators is effected through a set of registers and a controlled incrementing device. The set of registers includes a plurality of reference registers which store engine control data supplied from the digital processor. Another set of registers store respective sets of codes the values of which are sequentially and selectively incremented in accordance with a prescribed timing signal pattern during the rotation of the engine crankshaft. The data in these respective registers are compared with one another and upon the contents of a register, the contents of which are incremented by the timing signal pattern reaching the value stored in the reference register the data contained in which is supplied from the digital processor, an output is supplied to operate a respective engine actuator. Since the data supplied by the digital processor may vary at any time depending upon operating conditions, which are supplied by the digital processor, are not fixed but are subject to variation. If, at the time the digital processor is modifying or changing, namely updating, the data contained in a reference register, the value in a corresponding one of the second set of registers becomes equal to the old data with which it has been compared, no output signal is permitted to be supplied to an engine actuator until after the new data supplied by the digital processor has been input to the appropriate reference register. This preventing or inhibiting action enables the system to control the engine actuators in an extremely accurate manner, as the reference data upon which actuator control signals are ultimately based is always permitted to be dynamically updated so that the engine is always controlled on the basis of current engine conditions.
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公开(公告)号：US4173193A
公开(公告)日：1979-11-06
申请号：US866835
申请日：1978-01-04
CPC分类号： D05B69/26 , G05B19/042 , G05B2219/21136
摘要： An apparatus for controlling an electric sewing machine has a mechanism for transmitting the driving torque of a motor to the sewing machine to drive the same, a mechanism for imparting braking power to the sewing machine to stop the same, a mechanism for stopping the needle of said sewing machine at desired positions in its stroke and controlling means adapted to control these mechanisms. At least a part of the controlling means is constituted by a microcomputer. The signal input to the microcomputer is provided in synchronization with a synchronizing clock signal, and only such input signals as required in respective periods of operation are checked in each of the periods, so that the checking of the input signals is facilitated and accidents due to erroneous operation are avoided.
摘要翻译： 一种电动缝纫机的控制装置具有将电动机的驱动转矩传递给缝纫机进行驱动的机构，用于向缝纫机施加制动力以使其停止的机构， 所述缝纫机在其行程中的期望位置和适于控制这些机构的控制装置。 控制装置的至少一部分由微计算机构成。 输入到微计算机的信号与同步时钟信号同步地提供，并且在每个周期中仅检查在各个周期中所需的这样的输入信号，从而便于输入信号的检查和由于 避免了错误的操作。
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