公开(公告)号：US20210013119A1

公开(公告)日：2021-01-14

申请号：US17037542

申请日：2020-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L25/07 ,  H01L23/485 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US20200098690A1

公开(公告)日：2020-03-26

申请号：US16167501

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

公开(公告)号：US20200098659A1

公开(公告)日：2020-03-26

申请号：US16170067

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US10460980B2

公开(公告)日：2019-10-29

申请号：US15888072

申请日：2018-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

公开(公告)号：US20190206720A1

公开(公告)日：2019-07-04

申请号：US15888072

申请日：2018-02-04

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/311 ,  H01L21/763 ,  H01L21/761

Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.

公开(公告)号：US12249545B2

公开(公告)日：2025-03-11

申请号：US17407157

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/10 ,  H10B61/00 ,  H10B63/10 ,  H10N50/80 ,  H10N70/00

Abstract: An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US12087712B2

公开(公告)日：2024-09-10

申请号：US18123317

申请日：2023-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L21/56 ,  H01L21/71 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L21/71 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L2223/6661 ,  H01L2224/05624

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11894439B2

公开(公告)日：2024-02-06

申请号：US17068840

申请日：2020-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Heng-Ching Lin ,  Yu-Teng Tseng ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L29/4238 ,  H01L29/7835 ,  H01L21/26513

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

公开(公告)号：US11658118B2

公开(公告)日：2023-05-23

申请号：US17520725

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

CPC classification number: H01L23/5283 ,  H01L27/1203 ,  H01L27/124 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/7835 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/84 ,  H01L29/45 ,  H03F3/16 ,  H03F2200/294

Abstract: A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

公开(公告)号：US11205605B2

公开(公告)日：2021-12-21

申请号：US16840463

申请日：2020-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.