公开(公告)号：US10290640B1

公开(公告)日：2019-05-14

申请号：US15790035

申请日：2017-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou

IPC: H01L27/11 ,  G11C11/412

Abstract: A 6T SRAM cell includes a substrate having thereon a first pull-up (PU-1) transistor, a first pull-down (PD-1) transistor, a second pull-up (PU-2) transistor, and a second pull-down (PD-2) transistor. A first contact hard mask partially overlaps with a source diffusion region of the PU-1 transistor. A second contact hard mask partially overlaps with a first gate and a source diffusion region of the PD-1 transistor. A first contact plug partially lands on the first contact hard mask and partially lands on the source diffusion region of the PU-1 transistor. A second contact plug partially lands on the second contact hard mask and partially lands on the source diffusion region of the PD-1 transistor.

公开(公告)号：US10115786B2

公开(公告)日：2018-10-30

申请号：US15352551

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02 ,  H01G11/24

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

公开(公告)号：US10056493B2

公开(公告)日：2018-08-21

申请号：US15853875

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Chen-Bin Lin ,  Sanpo Wang ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

公开(公告)号：US09754828B1

公开(公告)日：2017-09-05

申请号：US15200000

申请日：2016-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/7831

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

公开(公告)号：US09608126B1

公开(公告)日：2017-03-28

申请号：US14953036

申请日：2015-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu ,  Xu Yang Shen ,  Zhibiao Zhou ,  Qinggang Xing

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

公开(公告)号：US09530834B1

公开(公告)日：2016-12-27

申请号：US14967344

申请日：2015-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L29/94 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a patterned first conductive layer on the material layer, forming a first dielectric layer on the patterned first conductive layer; forming a second conductive layer and a cap layer on the first dielectric layer; removing part of the cap layer to form a spacer on the second conductive layer; and using the spacer to remove part of the second conductive layer for forming a trench above the patterned first conductive layer and fin-shaped structures adjacent to the trench.

Abstract translation: 公开了制造电容器的方法。 该方法包括以下步骤：提供材料层; 在所述材料层上形成图案化的第一导电层，在所述图案化的第一导电层上形成第一介电层; 在所述第一介电层上形成第二导电层和盖层; 去除所述盖层的一部分以在所述第二导电层上形成间隔物; 以及使用间隔件去除用于在图案化的第一导电层上方形成沟槽的第二导电层的一部分和与沟槽相邻的鳍状结构。

公开(公告)号：US09412734B2

公开(公告)日：2016-08-09

申请号：US14588991

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/10 ,  H01L28/87 ,  H01L28/91

Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.

Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层，电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极，底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。