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    Semiconductor structure and manufacturing method thereof
    31.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11152484B2

    公开(公告)日：2021-10-19

    申请号：US16808180

    申请日：2020-03-03

    Applicant: United Microelectronics Corp.

    Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

    IPC: H01L29/66 ,  H01L21/768 ,  H01L27/12 ,  H01L29/06

    Abstract: A semiconductor structure including a substrate, a CMOS device and a BJT is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a first N-type doped region and a second N-type doped region disposed in the substrate. The PMOS transistor includes a first P-type doped region and a second P-type doped region disposed in the substrate. The BJT includes a collector, a base and an emitter. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A first metal silicide layer, a second metal silicide layer, and a third metal silicide layer are respectively located on the second side of the substrate and respectively disposed on the collector, the first N-type doped region, and the first P-type doped region.

    Semiconductor device and method for manufacturing the same
    35.
    发明授权
    Semiconductor device and method for manufacturing the same 有权

    公开(公告)号：US10903314B2

    公开(公告)日：2021-01-26

    申请号：US16017840

    申请日：2018-06-25

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Shen Li ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Xingxing Chen ,  Chee-Hau Ng

    IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/306 ,  H01L21/285

    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    37.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190252253A1

    公开(公告)日：2019-08-15

    申请号：US15928105

    申请日：2018-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Purakh Raj Verma ,  Su Xing ,  Ching-Yang Wen

    IPC: H01L21/768 ,  H01L27/12 ,  H01L23/48 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.

    SEMICONDUCTOR DEVICE
    38.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190221517A1

    公开(公告)日：2019-07-18

    申请号：US15893676

    申请日：2018-02-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

    IPC: H01L23/528 ,  H01L29/08 ,  H01L27/12 ,  H01L29/78

    Abstract: A semiconductor device on silicon-on-insulator (SOI) substrate includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

    Integrated circuit device
    39.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12249545B2

    公开(公告)日：2025-03-11

    申请号：US17407157

    申请日：2021-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

    IPC: H01L23/10 ,  H10B61/00 ,  H10B63/10 ,  H10N50/80 ,  H10N70/00

    Abstract: An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

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