公开(公告)号：US07608908B1

公开(公告)日：2009-10-27

申请号：US12125613

申请日：2008-05-22

申请人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

IPC分类号： H01L29/00 ,  H01L29/167

CPC分类号： H01L21/76264

摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).

摘要翻译： 为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。 一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。 发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置 层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。 通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss） （273,274; 273'，274'; 273“，”274“）上。 掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降， 距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。 在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875） 。

公开(公告)号：US20060273428A1

公开(公告)日：2006-12-07

申请号：US11144570

申请日：2005-06-02

申请人： Vishnu Khemka ,  Amitava Bose ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Ronghua Zhu

IPC分类号： H01L27/082

CPC分类号： H01L29/7393 ,  H01L29/063 ,  H01L29/66325

摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions (120) having the first conductivity type, a plurality of second semiconductor regions (130) having the first conductivity type, and a plurality of third semiconductor regions (140) having the second conductivity type. A sinker region (142) having the second conductivity type is disposed in a third semiconductor region and a first semiconductor region during manufacture to define the plurality of regions and tie the buried semiconductor region to the plurality of third semiconductor regions. An emitter (150) having the first conductivity type is disposed in one of the third semiconductor regions, a collector (170) having the first conductivity type is disposed in the other of the third semiconductor regions. A field poly plate (162) is provided and tied to the collector (170). In a particular embodiment, the plurality of third semiconductor regions and the buried semiconductor region deplete the plurality of first semiconductor regions in response to a reverse bias potential applied between the plurality of second semiconductor regions and the plurality of third semiconductor regions.

摘要翻译： 一种包括具有第一导电类型的半导体衬底（110）的绝缘栅双极型晶体管（IGBT）（100）和位于半导体衬底上方的具有第二导电类型的掩埋半导体区域（115）的半导体元件和制造方法。 IGBT还包括具有第一导电类型的多个第一半导体区域（120），具有第一导电类型的多个第二半导体区域（130）和具有第二导电类型的多个第三半导体区域（140）。 具有第二导电类型的沉降片区域（142）在制造期间设置在第三半导体区域和第一半导体区域中，以限定多个区域并将掩埋半导体区域与多个第三半导体区域相连。 具有第一导电类型的发射极（150）设置在第三半导体区域之一中，具有第一导电类型的集电极（170）设置在第三半导体区域中的另一个中。 提供了现场多晶板（162）并将其连接到集电器（170）。 在特定实施例中，响应于施加在多个第二半导体区域和多个第三半导体区域之间的反向偏置电位，多个第三半导体区域和掩埋半导体区域耗尽多个第一半导体区域。

公开(公告)号：US20060261382A1

公开(公告)日：2006-11-23

申请号：US11134792

申请日：2005-05-19

申请人： Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose

发明人： Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose

IPC分类号： H01L29/80

CPC分类号： H01L29/8611 ,  H01L29/063 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for reducing substrate leakage current of lateral RESURF diode devices. The diode device (60, 60′, 100) comprises first (39) and second (63) surface terminals overlying a semiconductor substrate (22) coupled to P (38, 32, 26) and N (24, 30, 46) type regions providing the diode action. An unavoidable parasitic vertical device (54, 92) permits leakage current to flow from the first terminal (39) to the substrate (22). This leakage current is reduced by having the diode device second terminal (63) comprise both N (46) and P (62) type regions coupled together by the second terminal (63). This forms a shorted base-collector lateral transistor (72) between the first (39) and second (63) terminals to provide the diode function. The gain of this lateral transistor (72) increases the proportion of first terminal (39) current that flows to the second terminal (63) rather than the substrate (22). In preferred embodiments, the first (39) or second (63) terminal is also ohmically coupled to a buried layer (24) that overlies the substrate (22) beneath the shorted base-collector lateral transistor (72).

摘要翻译： 提供了减少侧面RESURF二极管器件的衬底漏电流的方法和装置。 二极管器件（60,60'，100）包括覆盖耦合到P（38,32,26）和N（24,30,46）型的半导体衬底（22）上的第一（39）和第二（63） 提供二极管动作的区域。 不可避免的寄生垂直装置（54,92）允许泄漏电流从第一端子（39）流到衬底（22）。 通过使二极管器件的第二端子（63）包括由第二端子（63）耦合在一起的N（46）和P（62）型区域来减小漏电流。 这形成了在第一（39）和第二（63）端子之间的短路基极集电极横向晶体管（72），以提供二极管功能。 该横向晶体管（72）的增益增加流到第二端子（63）而不是衬底（22）的第一端子（39）电流的比例。 在优选实施例中，第一（39）或第二（63）端子也被欧姆耦合到覆盖短路基极 - 集电极横向晶体管（72）下面的衬底（22）的掩埋层（24）。

公开(公告)号：US20080293211A1

公开(公告)日：2008-11-27

申请号：US11752608

申请日：2007-05-23

申请人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd C. Roggenbauer

发明人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd C. Roggenbauer

IPC分类号： H01L21/20

CPC分类号： H01L29/94 ,  H01L27/13 ,  H01L28/91 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).

摘要翻译： 半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。 深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。 第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

公开(公告)号：US08963241B1

公开(公告)日：2015-02-24

申请号：US13460717

申请日：2012-04-30

申请人： Vishnu Khemka ,  Ronghua Zhu ,  Tahir Arif Khan ,  Bernhard Heinrich Grote

发明人： Vishnu Khemka ,  Ronghua Zhu ,  Tahir Arif Khan ,  Bernhard Heinrich Grote

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0653 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/7835

摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.

摘要翻译： 分离栅极功率晶体管包括掺杂衬底，衬底上的栅氧化层，以及形成多晶硅栅极和多晶硅场板的栅极氧化物层上的分裂多晶硅层。 两个多晶硅部分被间隙隔开。 场板电耦合到分离栅功率晶体管的源极。 一个或多个多晶硅延伸片从场板延伸到至少在第一掺杂区的边缘上方。 多晶硅栅极被切割以形成朝向主体衬底延伸的每个多晶硅延伸片的端部的切出区域。 一个或多个多晶硅延伸片将场板下面的过渡区域的部分强制为深度耗尽，从而防止在该区域中形成空穴反转层。

公开(公告)号：US08969958B1

公开(公告)日：2015-03-03

申请号：US13460603

申请日：2012-04-30

申请人： Vishnu Khemka ,  Ronghua Zhu ,  Tahir Arif Khan ,  Bernhard Heinrich Grote

发明人： Vishnu Khemka ,  Ronghua Zhu ,  Tahir Arif Khan ,  Bernhard Heinrich Grote

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate positioned over a channel region and a first portion of a transition region and a polysilicon field plate positioned over a second portion of the transition region and a shallow trench isolation region. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more body extension regions, each having the same doping type as the body substrate, extend at least underneath the edge of the field plate adjacent to the gap. The body extension regions force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.

摘要翻译： 分离栅功率晶体管包括掺杂衬底，衬底上的栅极氧化物层和栅极氧化物层上的分离多晶硅层，其形成位于沟道区域上的多晶硅栅极和过渡区域的第一部分以及多晶硅 位于过渡区域的第二部分上的场板和浅沟槽隔离区域。 两个多晶硅部分被间隙隔开。 场板电耦合到分离栅功率晶体管的源极。 每个具有与主体基板相同的掺杂类型的一个或多个本体延伸区域至少延伸到邻近间隙的场板的边缘的下方。 体延伸区域迫使场板下方的过渡区域的部分深度耗尽，从而防止在该区域中形成空穴反转层。

公开(公告)号：US08987818B1

公开(公告)日：2015-03-24

申请号：US13312827

申请日：2011-12-06

申请人： Joel Montgomery McGregor ,  Vishnu Khemka

发明人： Joel Montgomery McGregor ,  Vishnu Khemka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/402

摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.

摘要翻译： 分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。 多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区上的多晶硅栅极，以及形成在衬底的过渡区域的一部分上的多晶硅场板的第二部分。 两个多晶硅部分被间隙隔开。 将轻掺杂区域注入到间隙下方的衬底中，从而形成具有与衬底本体相同的掺杂类型的桥。 场板还在形成在衬底中的场氧化物填充沟槽上延伸。 场板电耦合到分离栅功率晶体管的源极。

公开(公告)号：US08946851B1

公开(公告)日：2015-02-03

申请号：US13446987

申请日：2012-04-13

申请人： Joel Montgomery McGregor ,  Vishnu Khemka

发明人： Joel Montgomery McGregor ,  Vishnu Khemka

IPC分类号： H01L23/58

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/402

摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.

摘要翻译： 分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，其具有作为第一掺杂区的相反类型的第一掺杂区和第二掺杂区，形成在衬底表面上的栅氧化层， 在栅极氧化物层上形成分裂的多晶硅层。 将多晶硅层切割成两个电隔离部分，形成位于衬底的沟道区域和过渡区域上方的多晶硅栅极的第一部分，以及形成在形成在场氧化物填充沟槽上的整个场中的多晶硅场板的第二部分 第二掺杂区域。 两个多晶硅部分被间隙隔开。 将轻掺杂区域注入到间隙下方的衬底中并与沟槽相邻，由此形成具有与第一掺杂区域相同的掺杂类型的填充区域。