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公开(公告)号：US4771249A
公开(公告)日：1988-09-13
申请号：US53653
申请日：1987-05-26
CPC分类号： H03L7/107 , H03L3/00 , H03L7/18 , H03L7/0893 , H03L7/0898
摘要： A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.
摘要翻译： 提供了具有可编程宽带窄带滤波器的锁相环（PLL）。 当PLL电路工作开始时，或当PLL的工作频率变化很大时，相位检测器起到强制滤波器处于宽频带模式以允许瞬态模式下的快速电路运行的作用。 在PLL输出稳定在预定频率附近之后，检测并计数在达到锁定状态之前输出频率在预定频率之上变化高于和低于该频率的次数。 在输出频率高于和低于预定频率预定次数之后，滤波器自动切换到低频带模式以允许PLL以稳定的方式操作。
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32.发明授权Integrated circuit having hardware circuitry to prevent electrical or thermal stressing of the silicon circuitry 有权具有用于防止硅电路的电应力或热应力的硬件电路的集成电路公开(公告)号：US06330668B1
公开(公告)日：2001-12-11
申请号：US09133946
申请日：1998-08-14
申请人： Andreas Curiger , Wendell L. Little
发明人： Andreas Curiger , Wendell L. Little
IPC分类号： G06F1130
CPC分类号： G06F21/75 , G05B19/0428 , G05B2219/24205 , G06F11/004 , G06F11/24 , G06F11/3013 , G06F11/3024 , G06F11/3058 , G06F21/71 , G06F21/72 , G06F2221/2101 , G06F2221/2143 , G06K19/073 , G06K19/07363
摘要： An integrated circuit, such as a microprocessor, which incorporates hardware mechanisms to prevent the circuitry from operating outside the proper bounds of design. The hardware circuitry prevents the microprocessor circuitry from being forced to operate at clock speeds that are greater than it is designed for, from operating at temperatures above or below that which it is designed for, and from being forced to operate at voltages that are above or below voltages that the microprocessor is designed to operate at.
摘要翻译： 诸如微处理器的集成电路，其集成了硬件机制以防止电路在设计的正确界限之外运行。 硬件电路防止微处理器电路被强制以比在其设计的温度高于或低于其设计的温度下工作的时钟速度操作，并且被强制在高于或高于 低于微处理器设计工作的电压。
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公开(公告)号：US06272637B1
公开(公告)日：2001-08-07
申请号：US08837145
申请日：1997-04-14
IPC分类号： H04L932
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/554 , G06F2207/7219 , G11C29/46
摘要： A microcontroller communicating via a data path and an address path with a memory block containing encrypted contents, the microcontroller including the capability for detecting resets effectuated in the wake of an unauthorized attempt to gain access to the encrypted contents and the capability of evading such an unauthorized attempt.
摘要翻译： 通过数据路径和地址路径与包含加密内容的存储块进行通信的微控制器，微控制器包括在未经授权的尝试访问加密内容之后实现的检测复位的能力，以及逃避这种未经授权的能力 尝试。
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公开(公告)号：US6014051A
公开(公告)日：2000-01-11
申请号：US156889
申请日：1998-09-18
申请人： Wendell L. Little
发明人： Wendell L. Little
CPC分类号： G06F1/324 , G06F1/08 , G06F1/32 , Y02B60/1217
摘要： A circuit, for incorporation into an electrical system, for providing a clock signal frequency to other circuitry such as a microprocessor and/or co-processor circuitry. The clock signal frequency varies its speed depending on the available voltage and current from a host power source. The circuit maximizes clock frequency by lowering the available voltage and increasing the available supply current. The circuit can therefore provide a higher clock speed and more current for switching transistors.
摘要翻译： 一种用于结合到电气系统中的电路，用于向诸如微处理器和/或协处理器电路的其它电路提供时钟信号频率。 时钟信号频率根据主机电源的可用电压和电流而改变其速度。 该电路通过降低可用电压并增加可用的电源电流来最大化时钟频率。 因此，电路可以为开关晶体管提供更高的时钟速度和更多的电流。
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公开(公告)号：US5218707A
公开(公告)日：1993-06-08
申请号：US264125
申请日：1988-10-28
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , Y02B60/1228 , Y02B60/1235
摘要： An integrated circuit wherein remapping logic permits the output-driver characteristics of a given pin to changed in software, by changing the data stored in a nonvolatile control bit.
摘要翻译： 一种集成电路，其中通过改变存储在非易失性控制位中的数据，重映射逻辑允许给定引脚的输出驱动器特性在软件中改变。
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36.发明授权Isolation gates to permit selective power-downs within a closely-coupled multi-chip system 失效隔离门允许紧密耦合的多芯片系统内的选择性掉电
公开(公告)号：US5182810A
公开(公告)日：1993-01-26
申请号：US359246
申请日：1989-05-31
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/22
摘要： A battery-backed ancillary power-management chip, in combination with a battery-backed microprocessor or microcontroller, permits a low-power system to achieve a zero-power standby mode with full nonvolatility. The ancillary chip contains transmission gates which can cut off the connection between two other chips if one of them is turned off. This avoids problems of power leakage, substrate pumping, etc., when two chips which are connected together can be independently powered up or powered down.Also provided is a portable data module, which includes a microprocessor and a large LCD display. The disclosed inventions permit the user to operate the display without powering up the microprocessor (to preserve a complex display, e.g. when the user has provided no inputs for a certain length of time), or to operate the microprocessor without the display (e.g. for data transfer or reduction operations).
摘要翻译： 电池支持的辅助电源管理芯片与电池支持的微处理器或微控制器相结合，允许低功耗系统实现具有完全非易失性的零功耗待机模式。 辅助芯片包含传输门，如果其中一个芯片关闭，它们可以切断两个其他芯片之间的连接。 当连接在一起的两个芯片可以独立上电或断电时，可以避免漏电，基板泵送等问题。 还提供了一种便携式数据模块，其包括微处理器和大型LCD显示器。 所公开的发明允许用户操作显示器而不加电微处理器（以保持复杂的显示，例如当用户在一定时间内没有提供输入）时，或者在没有显示器的情况下操作微处理器（例如，用于数据 转移或还原操作）。
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公开(公告)号：US4893271A
公开(公告)日：1990-01-09
申请号：US18761
申请日：1987-02-26
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , H03L7/107 , H03L7/183 , H03L7/0898 , Y02B60/1217
摘要： A microcomputer having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the requirements change, the synthesizer responds to provide only the frequency required. Thus, the power dissipated by the microcomputer system is minimized.
摘要翻译： 具有预定时钟脉冲频率要求的微型计算机从乘法型频率合成器接收脉冲，该乘法器利用小于预定要求的最大值的参考频率。 合成器响应于程序指令以产生足以满足立即执行编程任务的要求的时钟脉冲频率。 随着要求的变化，合成器响应仅提供所需的频率。 因此，微机系统耗散的功率被最小化。
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38.发明授权RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines 失效RAM具有通过同时选择所有行线快速清除数据的能力
公开(公告)号：US4890263A
公开(公告)日：1989-12-26
申请号：US200649
申请日：1988-05-31
申请人： Wendell L. Little
发明人： Wendell L. Little
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A Random Access Memory having a fast Clear operation includes a cell array (10) which has a plurality of memory cells arranged in rows and columns. Each of the rows is selected by word lines (12) and the data is output on column lines (14). Each of the word lines (12) is selected by a row decode circuit (20) or a Clear signal through OR gates (22). The Clear signal selects all of the word lines (12) such that each row in the cell array (10) is selected. The bit line associated with each column are pulled to ground through an N-channel transistor (36) and a bit line bar pulled high through a P-channel transistor (38). In addition, the V.sub.CC supply to the array (10) is decoupled from the memory cells by a P-channel transistor (40).
摘要翻译： 具有快速清除操作的随机存取存储器包括具有以行和列排列的多个存储单元的单元阵列（10）。 每行由字线（12）选择，数据在列线（14）上输出。 每个字线（12）由行解码电路（20）或清零信号通过或门（22）选择。 清除信号选择所有字线（12），使得选择单元阵列（10）中的每一行。 与每个列相关联的位线通过N沟道晶体管（36）被拉到地，而位线条通过P沟道晶体管（38）被拉高。 此外，阵列（10）的VCC电源由P沟道晶体管（40）与存储器单元解耦。
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公开(公告)号：US4749991A
公开(公告)日：1988-06-07
申请号：US054079
申请日：1987-05-21
CPC分类号： G08B3/1066 , H04W52/0283
摘要： In system capable of self turn-off, a circuit arrangement for providing a controlled turn-off includes a detecting circuit for detecting actuation of a turn-off switch, thereby providing a turn-off authorization signal. A turn-off protection circuit is coupled to the detecting circuit and a controller is coupled to the turn-off protect circuit and the detecting circuit. The controller disables the turn-off protect circuit when the turn-off authorization is received and present. The controller generates a turn-off signal for powering the system down after the turn-off protect circuit has been disabled.
摘要翻译： 在能够自我关闭的系统中，用于提供受控关断的电路装置包括用于检测关断开关的致动的检测电路，从而提供关断授权信号。 关断保护电路耦合到检测电路，并且控制器耦合到关断保护电路和检测电路。 当接收到关闭授权并存在时，控制器禁用关断保护电路。 关闭保护电路被禁用后，控制器产生一个关闭信号，用于向系统供电。
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40.发明授权Method and apparatus in a data processor for selectively disabling a power-down instruction 失效用于选择性地禁用掉电指令的数据处理器中的方法和装置
公开(公告)号：US4669059A
公开(公告)日：1987-05-26
申请号：US549956
申请日：1983-11-07
CPC分类号： G06F9/30083 , G06F1/24 , G06F1/26
摘要： A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The method and circuit allows the code to be stored in the control register once and only once between system resets.
摘要翻译： 一种允许具有断电指令的数据处理器的用户选择性地禁用掉电指令的方法。 在优选电路中，用户将特殊代码存储在控制寄存器中，指示禁用掉电指令。 在随后执行掉电指令时，处理器被代码禁止关闭提供系统时钟的振荡器。 方法和电路允许代码在系统复位之间一次性存储在控制寄存器中。
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