公开(公告)号：US07821083B2

公开(公告)日：2010-10-26

申请号：US12137796

申请日：2008-06-12

申请人： Wenwu Wang ,  Wataru Mizubayashi ,  Koji Akiyama

发明人： Wenwu Wang ,  Wataru Mizubayashi ,  Koji Akiyama

IPC分类号： H01L27/88

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/513

摘要： A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum ion to the silicon oxide film or an interface between the silicon oxide film and the silicon substrate by a heat treatment. A laminated film or a mixed film of hafnium oxide and aluminum oxide having a ratio of hafnium and aluminum ranging from about 2:8 to 8:2 is used as the high-k dielectric film. The heat treatment is performed at any temperature from about 500 to 1000° C. for any period of time from about 1 to 100 seconds.

摘要翻译： 半导体器件包括含有铝的介电常数大于氧化硅膜/氧化硅膜/硅衬底的介电常数的栅电极/高k电介质绝缘膜的结构，并且具有扩散层 通过热处理将铝原子或铝离子扩散到氧化硅膜或氧化硅膜和硅衬底之间的界面而形成。 作为高k电介质膜，使用层叠膜或铪和铝的比例为约2：8〜8：2的氧化铪和氧化铝的混合膜。 热处理在约500至1000℃的任何温度下进行约1至100秒的任何时间段。

公开(公告)号：US20080308865A1

公开(公告)日：2008-12-18

申请号：US12137796

申请日：2008-06-12

申请人： Wenwu Wang ,  Wataru Mizubayashi ,  Koji Akiyama

发明人： Wenwu Wang ,  Wataru Mizubayashi ,  Koji Akiyama

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/513

摘要： A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum ion to the silicon oxide film or an interface between the silicon oxide film and the silicon substrate by a heat treatment. A laminated film or a mixed film of hafnium oxide and aluminum oxide having a ratio of hafnium and aluminum ranging from about 2:8 to 8:2 is used as the high-k dielectric film. The heat treatment is performed at any temperature from about 500 to 1000° C. for any period of time from about 1 to 100 seconds.

摘要翻译： 半导体器件包括含有铝的介电常数大于氧化硅膜/氧化硅膜/硅衬底的介电常数的栅电极/高k电介质绝缘膜的结构，并且具有扩散层 通过热处理将铝原子或铝离子扩散到氧化硅膜或氧化硅膜和硅衬底之间的界面而形成。 作为高k电介质膜，使用层叠膜或铪和铝的比例为约2：8〜8：2的氧化铪和氧化铝的混合膜。 热处理在约500至1000℃的任何温度下进行约1至100秒的任何时间段。

公开(公告)号：US08685851B2

公开(公告)日：2014-04-01

申请号：US13139063

申请日：2011-01-27

申请人： Chao Zhao ,  Wenwu Wang

发明人： Chao Zhao ,  Wenwu Wang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L27/101 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L27/2436 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.

摘要翻译： 提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。 包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。 该方法提供了具有高可控性和提高设备性能的处理。

公开(公告)号：US20120238088A1

公开(公告)日：2012-09-20

申请号：US13513160

申请日：2011-09-28

申请人： Jinjuan Xiang ,  Wenwu Wang

发明人： Jinjuan Xiang ,  Wenwu Wang

IPC分类号： H01L21/285

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method for fabricating metal gates using a gate-last process, comprising: providing a substrate (20), the substrate comprising a gate trench (30); performing at least one metal layer deposition and one annealing on the surface of the substrate to fill a metal layer (32) in the gate trench; and removing the metal layer outside of the gate trench. This method can reduce the parasitic resistance of the gates and improve the reliability of the transistors.

摘要翻译： 一种使用最后工艺制造金属栅极的方法，包括：提供衬底（20），所述衬底包括栅极沟槽（30）; 在所述衬底的表面上执行至少一个金属层沉积和一个退火以填充所述栅极沟槽中的金属层（32）; 以及去除所述栅极沟槽外部的所述金属层。 该方法可以减小栅极的寄生电阻并提高晶体管的可靠性。

公开(公告)号：US20120190188A1

公开(公告)日：2012-07-26

申请号：US13379967

申请日：2011-02-28

申请人： Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

发明人： Chao Zhao ,  Wenwu Wang ,  Huicai Zhong

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for filling a gap includes: providing a semiconductor substrate, at least having an metal interconnect layer and an insulating dielectric layer on top of the underlying metal interconnect layer, the insulating dielectric layer having a gap; forming a diffusion bather layer and a seed layer sequentially in the gap and on a surface of the insulating dielectric layer outside the gap; forming a mask layer on a surface of the seed layer outside of the gap; and depositing a metal layer on the semiconductor substrate with the mask layer, the metal layer filling the gap.

摘要翻译： 用于填充间隙的方法包括：提供至少在下面的金属互连层的顶部上具有金属互连层和绝缘介电层的半导体衬底，绝缘介电层具有间隙; 在所述间隙中的间隙和所述绝缘介电层的表面上顺序地形成扩散洗礼层和种子层; 在所述间隙的外侧的种子层的表面上形成掩模层; 以及用所述掩模层在所述半导体衬底上沉积金属层，所述金属层填充所述间隙。

公开(公告)号：US20120181509A1

公开(公告)日：2012-07-19

申请号：US13143932

申请日：2011-02-23

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/66045 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.

摘要翻译： 提供石墨烯器件结构及其制造方法。 石墨烯器件结构包括：石墨烯层; 形成在所述石墨烯层上的栅极区域; 以及形成在所述栅极区域的一侧并与所述石墨烯层连接的掺杂半导体区域，其中所述掺杂半导体区域是所述石墨烯器件结构的漏极区域，并且形成在所述栅极区域一侧的所述石墨烯层是源极 石墨烯器件结构的区域。 可以通过掺杂半导体区域改善石墨烯器件结构的开/关比，而不增加石墨烯材料的带隙，从而可以增强石墨烯材料在CMOS器件中的适用性，而不降低石墨烯材料的载流子迁移率 和设备的速度。