公开(公告)号：US20110037141A1

公开(公告)日：2011-02-17

申请号：US12906652

申请日：2010-10-18

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L29/02

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US08519465B2

公开(公告)日：2013-08-27

申请号：US13553386

申请日：2012-07-19

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US07833875B2

公开(公告)日：2010-11-16

申请号：US11931571

申请日：2007-10-31

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L21/76

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

摘要翻译： 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US08481387B2

公开(公告)日：2013-07-09

申请号：US13188587

申请日：2011-07-22

申请人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

发明人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/3144 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521

摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

摘要翻译： 在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。 绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。 当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

公开(公告)号：US08008214B2

公开(公告)日：2011-08-30

申请号：US11639164

申请日：2006-12-15

申请人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

发明人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

IPC分类号： H01L21/31 ,  H01L21/461

CPC分类号： H01L21/3144 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521

摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

摘要翻译： 在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。 绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。 当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

公开(公告)号：US20070167030A1

公开(公告)日：2007-07-19

申请号：US11639164

申请日：2006-12-15

申请人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

发明人： Jung-Geun Jee ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

IPC分类号： H01L21/31

CPC分类号： H01L21/3144 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521

摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

摘要翻译： 在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。 绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。 当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

公开(公告)号：US20110275190A1

公开(公告)日：2011-11-10

申请号：US13188587

申请日：2011-07-22

申请人： Jung-Geun JEE ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

发明人： Jung-Geun JEE ,  Young-Jin Noh ,  Bon-Young Koo ,  Chul-Sung Kim ,  Hun-Hyeoung Leam ,  Woong Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/3144 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521

摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

摘要翻译： 在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。 绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。 当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

公开(公告)号：US20080057670A1

公开(公告)日：2008-03-06

申请号：US11931571

申请日：2007-10-31

申请人： Jung Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L21/76

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

摘要翻译： 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US07101803B2

公开(公告)日：2006-09-05

申请号：US10784326

申请日：2004-02-23

申请人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Seung-Mok Shin ,  Woo-Sung Lee

发明人： Sang-Hoon Lee ,  Hun-Hyeoung Leam ,  Seung-Mok Shin ,  Woo-Sung Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/76224

摘要： In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (N2O) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.

摘要翻译： 根据沟槽隔离的方法，在半导体衬底上形成第一氧化物层。 第一导电层和氮化物层依次形成在第一氧化物层上。 蚀刻氮化物层，第一导电层和第一氧化物层，以形成氮化物层图案，第一导电层图案和氧化物层图案。 蚀刻邻近第一导电层图案的衬底的一部分，以在衬底中形成沟槽。 沟槽在一氧化二氮（N 2 O 2 O）或一氧化氮（NO））气氛下固化。 通过原位工艺在沟槽中形成第二氧化物层。

公开(公告)号：US20070022941A1

公开(公告)日：2007-02-01

申请号：US11494566

申请日：2006-07-28

申请人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

发明人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

IPC分类号： C30B15/14

CPC分类号： C30B29/06 ,  C30B1/023

摘要： In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.

摘要翻译： 在形成具有较低电阻的层的方法和制造半导体器件的方法中，可以使用掺杂有杂质的非晶硅在单晶衬底上形成第一层。 可以在约550℃至约600℃的温度下对单晶衬底进行热处理，以将第一层转变成第二层，该第二层包括从第一层的下部变换的单晶硅膜 使所述单晶衬底和从所述第一层的上部变换的多晶硅膜接触。 可以通过选择性外延生长工艺在相对低的温度下形成该层，从而可以降低在高温过程中可能产生的对半导体器件的劣化或损坏。