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公开(公告)号：US20130009679A1
公开(公告)日：2013-01-10
申请号：US13178812
申请日：2011-07-08
申请人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
发明人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
IPC分类号： H03L7/06
摘要： In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.
摘要翻译： 在所描述的实施例中，具有数字爆炸相位检测器（BBPD）的时钟对准系统采用数字实现的滞后。 第一个BBPD被用于相位控制环路，该相位控制环路比较来自两个不同时钟域源的相位，其中一个时钟源源作为相位控制环路的参考时钟。 采用具有延迟参考时钟的第二个BBPD来解决第一个BBPD所看到的模糊相位关系。 检查被定义为第一BBPD和第二BBPD的当前值的矢量的BBPD矢量的初始状态。 基于BBPD矢量的初始状态和后续状态，允许非参考时钟通过相位控制回路的动作自然地移动到锁定状态，或者被迫使其相位顺时针或逆时针旋转以达到锁定状态。
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32.发明授权Methods and apparatus for evaluating the eye margin of a communications device using a data eye monitor 有权使用数据眼监视器评估通信设备的眼边的方法和装置公开(公告)号：US08126039B2
公开(公告)日：2012-02-28
申请号：US11434688
申请日：2006-05-16
IPC分类号： H04B3/46
CPC分类号： H04L1/20 , H04B17/309
摘要： Methods and apparatus are provided for evaluating the eye margin of a communications device using a data eye monitor. The quality of a data eye associated with a signal is evaluated by sampling the signal for a plurality of different phases; evaluating the samples to evaluate one or more of a height and width of the data eye; and determining whether the one or more of the height and width satisfy one or more predefined criteria. One or more parameters of the communications device can optionally be adjusted if the communications device does not satisfy the one or more predefined criteria. The communications device can optionally be assigned to a quality category based on the evaluation. A phase offset between a first clock signal used to sample the signal and one or more clocks used to sample data is reduced.
摘要翻译： 提供的方法和装置用于评估使用数据眼监护仪的通信设备的眼部边缘。 与信号相关联的数据眼的质量通过对多个不同相位的信号进行采样来评估; 评估样本以评估数据眼睛的高度和宽度中的一个或多个; 以及确定所述高度和宽度中的一个或多个是否满足一个或多个预定标准。 如果通信设备不满足一个或多个预定标准，则可以可选地调整通信设备的一个或多个参数。 可以根据评估可选地将通信设备分配给质量类别。 减少用于采样信号的第一时钟信号与用于采样数据的一个或多个时钟之间的相位偏移。
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33.发明授权公开(公告)号：US08081011B2
公开(公告)日：2011-12-20
申请号：US12843139
申请日：2010-07-26
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H02J1/00
摘要： Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.
摘要翻译： 公开了一种用于通过电源电路来调节提供给IC的电压的电路，该电源电路基于由电阻分压器产生的输出控制信号产生调节输出电压。 电路包括配置成产生接口控制信号的PVT检测器和连接到PVT检测器和电阻分压器的接口电路（i），以及（ii）被配置为响应于接口控制信号调整其电阻。 调整接口电路的电阻可以调节输出控制信号的电压，从而使电源电路调整稳压输出电压。
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公开(公告)号：US08067966B2
公开(公告)日：2011-11-29
申请号：US10999900
申请日：2004-11-30
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译： 公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。 电压控制延迟环路产生具有相似频率和不同相位的时钟信号。 电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。 多个延迟元件串联连接，例如循环。 在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。
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35.发明授权公开(公告)号：US07965133B2
公开(公告)日：2011-06-21
申请号：US12160373
申请日：2007-10-31
IPC分类号： G05F1/10
CPC分类号： H03K19/00369
摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要翻译： 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。
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公开(公告)号：US07912210B2
公开(公告)日：2011-03-22
申请号：US12187456
申请日：2008-08-07
IPC分类号： H04M1/00
CPC分类号： H04L25/0266 , H04M11/06
摘要： A system for improving the attenuation of an undesired signal found in a differential signal path through the use of inductive coupling. The system includes a primary inductor, a secondary inductor, and a filter. The primary inductor and the secondary inductor operably couple an input differential signal pair to an output differential signal pair, and the filter attenuates an undesired signal in the output differential signal pair.
摘要翻译： 一种用于通过使用电感耦合来改善在差分信号路径中发现的不期望信号的衰减的系统。 该系统包括初级电感器，次级电感器和滤波器。 主电感器和次级电感器将输入差分信号对可操作地耦合到输出差分信号对，并且滤波器衰减输出差分信号对中的不期望信号。
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37.发明申请公开(公告)号：US20100289476A1
公开(公告)日：2010-11-18
申请号：US12843139
申请日：2010-07-26
IPC分类号： H02J4/00
CPC分类号： H02J1/00
摘要： Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.
摘要翻译： 公开了一种用于通过电源电路来调节提供给IC的电压的电路，该电源电路基于由电阻分压器产生的输出控制信号产生调节输出电压。 电路包括配置成产生接口控制信号的PVT检测器和连接到PVT检测器和电阻分压器的接口电路（i），以及（ii）被配置为响应于接口控制信号调整其电阻。 调整接口电路的电阻可以调节输出控制信号的电压，从而使电源电路调整稳压输出电压。
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公开(公告)号：US07773667B2
公开(公告)日：2010-08-10
申请号：US11181286
申请日：2005-07-14
CPC分类号： G01R31/31715
摘要： The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
摘要翻译： 本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置（SERDES）的异步测试的装置，系统和方法。 示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟，其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器，其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。 在另外的实施例中，伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。
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39.发明申请公开(公告)号：US20100176856A1
公开(公告)日：2010-07-15
申请号：US12730671
申请日：2010-03-24
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译： 公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。
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40.发明授权Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers 有权具有DC偏移消除电路的模拟放大器和模拟放大器的偏移消除方法公开(公告)号：US07755421B2
公开(公告)日：2010-07-13
申请号：US12437860
申请日：2009-05-08
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译： 具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，耦合到输入节点的偏置电路; 和多个电流源。 所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿
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