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    Method to form and/or isolate vertical transistors
    32.
    发明授权
    Method to form and/or isolate vertical transistors 有权
    形成和/或隔离垂直晶体管的方法

    公开(公告)号：US06511884B1

    公开(公告)日：2003-01-28

    申请号：US09972503

    申请日：2001-10-09

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66666 ,  H01L29/7827

    摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.

    摘要翻译： 一种制造隔离垂直晶体管的方法，包括以下步骤。 提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。 该晶片还包括在中心晶体管区域两侧的STI区域。 将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。 具有侧壁的立柱。 在晶片上形成衬垫介质层，衬在垂直柱上。 在焊盘介电层上形成氮化物层。 该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。 图案化的氮化物和焊盘介电层被去除。 去除图案化的硬掩模。 栅极氧化物生长在晶片和垂直柱的暴露部分上。 在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。 间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的 垂直晶体管。

    Method to form a recessed source drain on a trench side wall with a replacement gate technique
    34.
    发明授权
    Method to form a recessed source drain on a trench side wall with a replacement gate technique 有权
    用替代栅极技术在沟槽侧壁上形成凹陷源极漏极的方法

    公开(公告)号：US06380088B1

    公开(公告)日：2002-04-30

    申请号：US09764241

    申请日：2001-01-19

    申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    IPC分类号： H01L21302

    CPC分类号： H01L29/66583 ,  H01L21/76224 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636

    摘要： An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

    摘要翻译： 一种改进的MOS晶体管和制造改进的MOS晶体管的方法。 MOS晶体管，具有沟槽侧壁上的凹陷源极漏极，具有替代栅极技术。 在浅沟槽隔离件中形成孔，其在有源区域中暴露衬底的侧壁。 在孔的有源区域中掺杂衬底的侧壁。 然后在孔中形成导电材料，并且导电材料变成源区和漏区。 然后去除蚀刻停止层，暴露导电材料的侧壁，并且对导电材料的暴露侧壁进行氧化预处理。 垫片形成在衬垫氧化物的顶部和导电材料的氧化部分的侧壁上。 衬垫氧化物层从结构中移除，但不从衬垫下方移除。 在间隔物之间​​的有源区域中的基板上形成栅极电介质层; 并且在所述栅极电介质层上形成栅电极。

    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
    36.
    发明授权
    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide 失效
    通过使氧化物的接触使S / D接触来形成升高的S / D CMOS器件的方法

    公开(公告)号：US06306714B1

    公开(公告)日：2001-10-23

    申请号：US09713802

    申请日：2000-11-16

    申请人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    发明人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    IPC分类号： H01L21336

    CPC分类号： H01L21/76877 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/66583 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

    摘要翻译： 制造用于MOS器件的升高的源极/漏极（S / D）的方法。 在衬底上形成具有栅极开口和源极/漏极开口的第一绝缘层。 我们形成了在第一绝缘层上的源/漏开口上方具有开口的LDD抗蚀剂掩模。 离子通过源极/漏极开口植入。 在栅极开口和源极/漏极开口中的基板上形成第一电介质层。 栅极形成在源极/漏极开口中的栅极开路和升高的源极/漏极（S / D）块中。 我们移除间隔块以形成间隔块开口。 我们通过将离子注入间隔块开口形成第二LDD区域。 我们在间隔块开口中形成第二间隔块。 插头开口通过凸起的源极/漏极（S / D）块形成。 接触塞以形式的塞子开口形成。

    Transistors with low overlap capacitance
    38.
    发明授权
    Transistors with low overlap capacitance 有权
    具有低重叠电容的晶体管

    公开(公告)号：US06297106B1

    公开(公告)日：2001-10-02

    申请号：US09307205

    申请日：1999-05-07

    申请人： Yang Pan ,  Erzhuang Lui

    发明人： Yang Pan ,  Erzhuang Lui

    IPC分类号： H01L21336

    CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/7833

    摘要： This invention relates to the fabrication of intergrated circuit devices and more particularly to a method for reducing the gate to drain and gate to source overlap capacitance of deep sub-micron CMOS devices, as an improved means of reducing device switching times. This is accomplished by customizing the gate insulating layer, such that the dielectric constant, K, is lower in the gate to drain and gate to source overlap regions, relative to the more centrally located gate region between the source and drain. This invention avoids the process control problems associated with using conventional post polysilicon gate oxidation as a means of lowering such overlap capacitance, particularly for the deep sub-micron regime.

    摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于减少深亚微米CMOS器件的栅极到漏极和栅极与源极重叠电容的方法，作为减少器件切换时间的改进方法。 这通过定制栅极绝缘层来实现，使得相对于源极和漏极之间更位于中心的栅极区域，介电常数K在栅极到漏极和栅极到源极重叠区域中较低。 本发明避免了与使用常规的后多晶硅栅极氧化相关的过程控制问题，作为降低这种重叠电容的手段，特别是对于深亚微米状态。

    Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors
    39.
    发明授权
    Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors 有权

    公开(公告)号：US06284581B1

    公开(公告)日：2001-09-04

    申请号：US09252626

    申请日：1999-02-18

    申请人： Yang Pan ,  Erzhuang Liu

    发明人： Yang Pan ,  Erzhuang Liu

    IPC分类号： H01L218238

    CPC分类号： H01L21/8249

    摘要： Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

    Way to fabricate the self-aligned T-shape gate to reduce gate resistivity
    40.
    发明授权
    Way to fabricate the self-aligned T-shape gate to reduce gate resistivity 失效
    制造自对准T型栅极以降低栅极电阻率的方法

    公开(公告)号：US6159781A

    公开(公告)日：2000-12-12

    申请号：US165004

    申请日：1998-10-01

    申请人： Yang Pan ,  Erzhuang Liu

    发明人： Yang Pan ,  Erzhuang Liu

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/338

    CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7833

    摘要： Disclosed is a method of fabricating a semiconductor field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact portion for low gate resistance. Salicides are formed on the T-gate source on drain contact areas resulting in large, low resistance contact areas.

    摘要翻译： 公开了制造半导体场效应晶体管的方法，其中栅极具有与半导体衬底接触的短脚部，其栅极长度短，结果为低电容，并且用于低栅极电阻的接触部分中的大量金属 。 在漏极接触区域的T型栅极源上形成杀菌剂，导致大的低电阻接触面积。