公开(公告)号：US20120287724A1

公开(公告)日：2012-11-15

申请号：US13105276

申请日：2011-05-11

申请人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0433 ,  G11C16/32 ,  G11C16/3454

摘要： A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.

摘要翻译： 提供了一种编程存储器的方法。 存储器具有第一单元，具有与第二单元共用的第一S / D区和第二S / D区。 第二单元具有与第二S / D区相反的第三S / D区。 当对第一单元进行编程时，第一电压被施加到第一单元的控制栅极，第二电压被施加到第二单元的控制栅极，以稍微导通第二单元的沟道，第三和第四电压 分别施加到第一和第三S / D区域，并且第二S / D区域是浮置的。 载体从第三S / D区流向第一S / D区，并通过源侧注入注入第一单元的电荷存储层。

公开(公告)号：US07864594B2

公开(公告)日：2011-01-04

申请号：US12250766

申请日：2008-10-14

申请人： Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

发明人： Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.

摘要翻译： 提供了一种用于编程非易失性存储器单元的存储装置，控制器及其方法。 存储装置包括多个存储单元，其中每个存储单元与相邻的存储单元共享源/漏区。 该方法利用施加到两个存储单元之间的源极/漏极区域中的补偿电子流，以提供足够的电子流来编程两个存储器单元之一，即使在另一个存储单元具有较大的阈值电压的情况下， 存储器单元的编程速度的偏差减小。

公开(公告)号：US20100176437A1

公开(公告)日：2010-07-15

申请号：US12352947

申请日：2009-01-13

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L29/4234 ,  H01L29/792

摘要： The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.

摘要翻译： 本发明提供一种存储器阵列。 存储器阵列包括衬底，多个字线，电荷俘获结构，多个沟槽沟道和多个位线。 字线位于衬底上，字线彼此平行。 电荷捕获结构覆盖每条字线的表面。 沟槽沟槽位于衬底之上，并且字线和沟槽沟槽交替布置，并且通过电荷捕获结构将每个沟槽沟道与相邻字线分开。 位线位于字线之上，并且每个位线跨越每一个字线，并且每个沟道沟道电耦合到位线。

公开(公告)号：US07754544B2

公开(公告)日：2010-07-13

申请号：US12570147

申请日：2009-09-30

申请人： Ta-Wei Lin ,  Wen-Jer Tsai

发明人： Ta-Wei Lin ,  Wen-Jer Tsai

IPC分类号： H01L21/8242

CPC分类号： H01L27/10802 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

摘要翻译： 提供了一种动态随机存取存储单元及其制造方法。 首先，提供形成有底部氧化物层和半导体层的基板。 半导体层形成在底部氧化物层上。 接下来，在半导体层上形成栅极。 然后，对半导体层进行图案化以暴露底部氧化物层的一部分。 之后，在半导体层的侧壁形成绝缘层，其中绝缘层的高度比半导体层的高度短，从而在绝缘层的顶部和半导体层之间形成间隙。 此外，在底部氧化物层上形成覆盖绝缘层并且与半导体层具有相同高度的掺杂层。 掺杂层经由间隙与半导体层的侧壁接触。

公开(公告)号：US06563752B2

公开(公告)日：2003-05-13

申请号：US09945289

申请日：2001-08-30

申请人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50

摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.

摘要翻译： 用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。 估计在预期寿命期内相对于存储器阵列的编程电压。 根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。 在加速测试电压下进行测试时间。 测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。 如果编程状态保持不变，则判断存储器阵列具有使用寿命。 如果编程状态不存在，则判断存储器阵列没有寿命周期。

公开(公告)号：US08796754B2

公开(公告)日：2014-08-05

申请号：US13166144

申请日：2011-06-22

申请人： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

发明人： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.

摘要翻译： 提供包括存储单元的存储器结构，并且存储单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US08674424B2

公开(公告)日：2014-03-18

申请号：US13304378

申请日：2011-11-24

申请人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Chih-Chieh Cheng

发明人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Chih-Chieh Cheng

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  G11C16/0458 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.

摘要翻译： 描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。 栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。 每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分 所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

公开(公告)号：US08664709B2

公开(公告)日：2014-03-04

申请号：US12839559

申请日：2010-07-20

申请人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Jyun-Siang Huang

发明人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Jyun-Siang Huang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.

摘要翻译： 提供包括衬底，堆叠栅极结构，两个掺杂区域和多个间隔物的非易失性存储器。 堆叠的栅极结构设置在衬底上，其中堆叠的栅极结构包括从底部到顶部相对于衬底的顺序的第一介电层，电荷存储层，第二介电层和导电层。 掺杂区域分别设置在堆叠栅极结构的两侧的衬底中，并且掺杂区域的底部部分在掺杂区域下与衬底接触。 间隔物分别设置在每个掺杂区域和衬底的每一侧之间，并且间隔物的顶部部分低于掺杂区域的顶部部分。

公开(公告)号：US20130134498A1

公开(公告)日：2013-05-30

申请号：US13304380

申请日：2011-11-24

申请人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

发明人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

摘要： A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.

摘要翻译： 描述了存储器件，包括衬底上的隧道介电层，隧道介电层上的栅极，栅极和隧道介电层之间的至少一个电荷存储层，栅极旁边的衬底中的两个掺杂区域，以及 字线，其设置在栅极上并电连接到栅极并且具有大于栅极的厚度的厚度。

公开(公告)号：US08399326B2

公开(公告)日：2013-03-19

申请号：US12785500

申请日：2010-05-24

申请人： Ta-Wei Lin ,  Wen-Jer Tsai

发明人： Ta-Wei Lin ,  Wen-Jer Tsai

IPC分类号： H01L21/336 ,  H01L21/311

CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802

摘要： Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.

摘要翻译： 公开了一种存储装置及其操作方法。 存储器件可以包括第一掺杂剂类型的源极区域和漏极区域，源极区域和漏极区域包含第一半导体材料; 所述主体区域被夹在所述源极和漏极区域之间，所述主体包括第二半导体材料; 至少在所述身体区域上的栅介电层; 以及包括在所述栅极介电层上的导电材料的栅极。 具体地，第一半导体材料和第二半导体材料之一与第一半导体材料和第二半导体材料中的另一个晶格匹配，并且具有小于第一半导体材料和第二半导体材料中的另一个的能隙的能隙 半导体材料。