公开(公告)号：US20100230738A1

公开(公告)日：2010-09-16

申请号：US12400828

申请日：2009-03-10

Applicant: Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

Inventor： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC: H01L29/788 ,  H01L21/336 ,  H01L29/00

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42324

Abstract: In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

Abstract translation: 在制造NOR闪速存储器结构的方法中，执行高掺杂离子注入工艺以形成与轻掺杂漏极区重叠的高度掺杂的漏极区。 因此，在用于形成接触孔的蚀刻工艺期间，闪速存储器结构可以具有减小的漏极结深度以改善短沟道效应，同时保护轻掺杂漏极区域不被穿孔。

公开(公告)号：US07632749B1

公开(公告)日：2009-12-15

申请号：US10823970

申请日：2004-04-13

Applicant: Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

Inventor： Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

IPC: H01L21/44

CPC classification number: H01L21/76816 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14

Abstract: A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

Abstract translation: 公开并提供了半导体器件。 半导体器件包括具有周边区域和中心区域的焊盘金属层。 此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。 此外，在焊盘金属层和下金属层之间形成层间电介质。 在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。 通孔电连接焊盘金属层和下部金属层。 另外，通孔位于垫金属层的周边区域的下方。

公开(公告)号：US07408220B2

公开(公告)日：2008-08-05

申请号：US11463250

申请日：2006-08-08

Applicant: Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

Inventor： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC: H01L29/788

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

Abstract translation: 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US20070026609A1

公开(公告)日：2007-02-01

申请号：US11463250

申请日：2006-08-08

Applicant: Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

Inventor： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

Abstract translation: 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07157333B1

公开(公告)日：2007-01-02

申请号：US11180117

申请日：2005-07-11

Applicant: Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

Inventor： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

Abstract translation: 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07078749B1

公开(公告)日：2006-07-18

申请号：US10618156

申请日：2003-07-11

Applicant: Jean Yee-Mei Yang ,  Yider Wu

Inventor： Jean Yee-Mei Yang ,  Yider Wu

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  G02F1/1334 ,  H01L29/792

Abstract: According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.

Abstract translation: 根据一个实施例，存储器结构包括具有位于源极区域和漏极区域之间的沟道区域的衬底。 存储器结构还包括形成在衬底的沟道区上的栅极层和形成在栅极层和衬底上的可调谐层间电介质。 可调谐层间电介质具有透明状态和不透明状态，并且包括位于基体内的矩阵和电或磁性可调谐材料。 在透明状态期间，紫外线可以通过可调谐层间电介质到达栅极层，例如进行UV擦除操作。 在不透明状态期间，防止紫外线通过可调谐层间电介质到栅极层，从而保护栅极层免于不必要的电荷存储和在各种过程中可能发生的外在损伤。

公开(公告)号：US07019366B1

公开(公告)日：2006-03-28

申请号：US10758173

申请日：2004-01-14

Applicant: Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

Inventor： Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

IPC: H01L23/62

CPC classification number: H01L27/0251

Abstract: More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.

Abstract translation: 通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。 焊盘区域包括在其上方具有第一金属层的基板。 第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。 电介质层分离第一和第二金属层。 电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。 随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度 通过组件。

公开(公告)号：US06897533B1

公开(公告)日：2005-05-24

申请号：US10247641

申请日：2002-09-18

Applicant: Jean Yee-Mei Yang ,  Yider Wu

Inventor： Jean Yee-Mei Yang ,  Yider Wu

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/02

CPC classification number: H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

Abstract: A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.

Abstract translation: 提出了一种非易失性多位存储单元，其包括源极，漏极，耦合源极和漏极的沟道以及具有多个电荷俘获区域的栅极，所述多个电荷俘获区域被定位成使得每个电荷俘获区域中的俘获电荷为 能够影响栅极电压对通道中电子流的影响。 电荷捕获区域处于多层氧化物/氮化物/氧化物中，并且可以有多个电荷俘获区域。 电荷存储在氮化物层中并被氧化层隔离。

公开(公告)号：US06767791B1

公开(公告)日：2004-07-27

申请号：US10364569

申请日：2003-02-10

Applicant: Yider Wu ,  Harpreet K. Sachar ,  Jean Yee-Mei Yang

Inventor： Yider Wu ,  Harpreet K. Sachar ,  Jean Yee-Mei Yang

IPC: H01L21336

CPC classification number: H01L29/511 ,  H01L21/28273 ,  H01L29/42324

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.

Abstract translation: 根据一个示例性实施例，一种结构包括基底。 该结构还包括隧道氧化物层，其中隧道氧化物层位于衬底上。 该结构还包括位于隧道氧化物层上的浮置栅极，其中浮栅包括氮。 浮栅可以进一步包括多晶硅，并且例如可以位于浮动栅闪存单元中。 例如，氮可以抑制隧道氧化物层的第一和第二端区域的氧化物生长。 可以将氮气注入浮栅中，例如以约10 13个原子/ cm 2和约10 15个原子/ cm 2的浓度注入。 根据该示例性实施例，该结构还包括位于浮动栅极上方的ONO堆叠。 该结构还可以包括位于ONO堆叠上的控制门。

公开(公告)号：US06706595B2

公开(公告)日：2004-03-16

申请号：US10100485

申请日：2002-03-14

Applicant: Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

Inventor： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

Abstract translation: 用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 生长自杀剂不会使第一和第二位线短路。