公开(公告)号：US07005698B2

公开(公告)日：2006-02-28

申请号：US10668902

申请日：2003-09-23

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US06818948B2

公开(公告)日：2004-11-16

申请号：US10621597

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L2976

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A split gate flash memory device and method of fabricating the same. A cell of the split gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 一种分闸式闪存装置及其制造方法。 根据本发明的分裂栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

公开(公告)号：US06781191B2

公开(公告)日：2004-08-24

申请号：US10621431

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L29788

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06734066B2

公开(公告)日：2004-05-11

申请号：US10307704

申请日：2002-12-02

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L21336

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US06562673B2

公开(公告)日：2003-05-13

申请号：US09948530

申请日：2001-09-07

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L218238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating a memory cell of self-aligned split gate flash memory first provides a substrate having an active area. A first gate insulating layer, a conductive layer and a buffer layer are formed within the active area. A portion of the buffer layer is removed to form a first opening. A buffer spacer is formed on the side walls of the first opening. A portion of the conductive layer and first gate insulating layer under the first opening are removed to form a second opening. The contact spacers, the source region and the contact plug are formed in the second opening in sequence. After the buffer spacers are removed, a third opening is formed. The bottom surface of the third opening and the top surface of the contact plug are oxidized to form the oxide layers. Another buffer spacers fill the third opening. The remaining buffer layer is removed to form the fourth opening. The conductive layer under the bottom of the fourth opening is removed, except the portion under the oxide layer, to form the floating gates. After the formation of a second gate insulating layer, the control gates and the control gate spacers are formed in sequence.

公开(公告)号：US06511881B1

公开(公告)日：2003-01-28

申请号：US10191722

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for fabricating split gate flash memory cell. The method includes sequentially forming conductive layers and insulating layers on a semiconductor substrate, followed by forming a first opening in the conductive layers and the insulating layers. Next, a shallow trench isolation is defined in the first opening and an insulating layer is defined simultaneously in the active area within the shallow trench isolation to form a first gate isolation layer. Then, a conductive sidewall layer is formed on the sidewalls of the first gate insulating layer. The first gate insulating layer and the conductive sidewall layer are used as a hard mask to remove the conductive layer not covered by the hard mask, thus forming a floating gate comprised of the conductive sidewall layer and the conductive layer underneath. A second gate insulating layer, control gate and source/drain are then formed conventionally.

Abstract translation: 一种用于制造分流栅闪存单元的方法。 该方法包括在半导体衬底上依次形成导电层和绝缘层，随后在导电层和绝缘层中形成第一开口。 接下来，在第一开口中限定浅沟槽隔离，并且在浅沟槽隔离中的有源区域中同时限定绝缘层，以形成第一栅极隔离层。 然后，在第一栅极绝缘层的侧壁上形成导电侧壁层。 第一栅绝缘层和导电侧壁层用作硬掩模以去除未被硬掩模覆盖的导电层，从而形成由导电侧壁层和下面的导电层组成的浮栅。 然后通常形成第二栅极绝缘层，控制栅极和源极/漏极。

公开(公告)号：US07056792B2

公开(公告)日：2006-06-06

申请号：US10819464

申请日：2004-04-06

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 堆叠式栅极闪存器件及其制造方法。 根据本发明的堆叠式栅极闪存器件的单元被布置在衬底内的单元沟槽中以实现存储单元的更高集成度。

公开(公告)号：US06734686B2

公开(公告)日：2004-05-11

申请号：US10118778

申请日：2002-04-08

Applicant: Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

Inventor： Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

IPC: G01R2726

CPC classification number: G01F23/268 ,  G01F23/263 ,  G01F23/266 ,  G01N27/226

Abstract: This invention relates to a method for detecting quantity variation of high purity liquid chemicals by way of detecting capacitance variation to determine the liquid level of liquid chemicals. Meanwhile, the ratio of the area of the smallest electrode of the capacitor to the distance between the electrodes is adjusted to magnify the capacitance so that a very small variation can be observed clearly. This invention also discloses a device to carry out this method.

Abstract translation: 本发明涉及一种用于通过检测电容变化来检测高纯度液体化学品的量变化以确定液体化学品的液位的方法。 同时，电容器的最小电极的面积与电极之间的距离的比率被调节以放大电容，使得可以清楚地观察到非常小的变化。 本发明还公开了一种执行该方法的装置。

公开(公告)号：US06642116B2

公开(公告)日：2003-11-04

申请号：US10191108

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method of fabricating flash memory cell is described. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a buffer layer; removing portions of the buffer layer to farm a floating gate insulating layer; forming a second conductive layer; removing portions of the first conductive layer and the second conductive layer, such that the second conductive layer forms conductive spacers having conductive tips situated at the tips, and the floating gate insulating layer, the floating gate and the first gate insulating layer are combined as a floating gate region; forming a second insulating layer; forming a third conductive layer; removing portions of the third conductive layer and the second insulating layer to form a control gate, a second gate insulating layer, a first opening and a second opening; forming a source region on the substrate; forming spacers; and forming a drain region on the substrate.

Abstract translation: 描述了一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 形成第一导电层; 形成缓冲层; 去除所述缓冲层的部分以形成浮栅绝缘层; 形成第二导电层; 去除所述第一导电层和所述第二导电层的部分，使得所述第二导电层形成具有位于所述尖端处的导电尖端的导电间隔物，并且所述浮栅绝缘层，所述浮栅和所述第一栅极绝缘层被组合为 浮动栅区; 形成第二绝缘层; 形成第三导电层; 去除所述第三导电层和所述第二绝缘层的部分以形成控制栅极，第二栅极绝缘层，第一开口和第二开口; 在所述基板上形成源极区域; 形成间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US5989952A

公开(公告)日：1999-11-23

申请号：US934617

申请日：1997-09-22

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

IPC: C12Q1/48 ,  H01L21/02 ,  H01L21/8242 ,  H01L12/8242

CPC classification number: H01L28/92 ,  C12Q1/48 ,  H01L27/10852

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造具有冠型电容器的DRAM单元的方法。 该方法包括以下步骤：（a）在半导体衬底上形成晶体管; （b）在所述晶体管上形成绝缘层; （c）选择性地蚀刻绝缘层以形成接触开口; （d）在所述绝缘层上形成第一导电层并填充到所述接触开口中; （e）在所述第一导电层上形成蚀刻停止层和掩​​模层; （f）图案掩模层以形成多个开口; （g）在掩模层的侧壁上形成电介质间隔物，去除蚀刻停止层的暴露部分; （h）通过使用电介质间隔物作为掩模，各向异性地蚀刻掩模层和第一导电层，分别暴露蚀刻停止层和绝缘层; （i）去除未覆盖的蚀刻停止层以暴露第一导电层; （j）通过使用电介质间隔物作为掩模，将第一导电层各向异性蚀刻到预定深度，由此形成冠型存储电极; （k）去除电介质间隔物和蚀刻停止层; （l）在所述存储电极的暴露部分上形成介电层; 和（m）在所述电介质层上形成作为相对电极的第二导电层。