公开(公告)号：US5854561A

公开(公告)日：1998-12-29

申请号：US957426

申请日：1997-10-24

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  G05F3/16 ,  H03K17/16

CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换装置包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

公开(公告)号：US5838627A

公开(公告)日：1998-11-17

申请号：US768090

申请日：1996-12-16

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C29/26 ,  G11C29/34 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C29/26 ,  G11C29/34 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10

摘要： Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

摘要翻译： 数据输入/输出焊盘部分对应于存储块并且与存储块和存储块之间的中心区域中相应的存储块相邻布置。 电源垫布置在中心区域的两端。 电源板将电源电压发送到数据输入/输出焊盘部分，电源焊盘将电源电压发送到数据输入/输出焊盘部分。 用于外围电路的电源板布置在中心区域的中心部分。 为每个存储块提供多位测试电路。 在大容量存储装置中实现高速稳定运行的数据输入/输出缓冲器，其又适应多位测试模式。

公开(公告)号：US5646900A

公开(公告)日：1997-07-08

申请号：US583893

申请日：1996-01-11

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/419

CPC分类号： G11C7/065 ,  G11C5/146

摘要： N channel sense amplifier transistors have their backgate potentials set to a backgate precharge potential higher than a potential intermediate between an operation power supply potential and a ground potential prior to start of sensing operation, and then lowered following the lowering of an n common source node potential during the sensing operation. The n common source node is precharged to the intermediate potential. The backgate precharge potential is set no greater than a potential of the intermediate potential plus a pn junction diffusion, to suppress a leakage current from the backgate to source or drain of each of the sense amplifier transistors. P channel sense amplifier transistors have also their backgate potential set to a precharge potential lower than the intermediate potential prior to sensing operation and raised following the rise of a p common source node potential.

摘要翻译： N沟道读出放大器晶体管的背栅电位被设置为比开始感测操作之前的工作电源电位和地电位之间的电位中间高的后栅极预充电电位，然后在n个共同源节点电位降低之后降低 在感测操作期间。 n个公共源节点被预充电到中间电位。 背栅预充电电位被设定为不大于中间电位加上pn结扩散的电位，以抑制从每个读出放大器晶体管的背栅到源极或漏极的漏电流。 P沟道读出放大器晶体管在其感测操作之前也将其背栅电位设置为低于中间电位的预充电电位，并且随着p共同源节点电位的上升而升高。

公开(公告)号：US5610533A

公开(公告)日：1997-03-11

申请号：US350064

申请日：1994-11-29

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  H03K17/16

CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换装置包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

公开(公告)号：US06643208B2

公开(公告)日：2003-11-04

申请号：US10347220

申请日：2003-01-21

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C00700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in access with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 变频器作为工作电源电压VCL1和VSL2或电压VCL2和VSL1，在待机周期和激活循环中的输出信号的逻辑电平进行访问。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US06246625B1

公开(公告)日：2001-06-12

申请号：US09497199

申请日：2000-02-03

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US5856951A

公开(公告)日：1999-01-05

申请号：US864756

申请日：1997-05-29

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/147

摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.

摘要翻译： 在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路 线。 虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。 电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者 二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

公开(公告)号：US5825705A

公开(公告)日：1998-10-20

申请号：US839834

申请日：1997-04-17

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/403 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/402

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C5/147

摘要： A timing generating circuit generates a signal SRE defining a period in which a self-refreshing operation is carried out based on a signal extRAS and a signal extCAS. An internal voltage down-converting circuit controls the level of an internal power supply voltage intVcc to be generated in the period defined by the signal SRE lower in the self-refreshing operation than in a normal operation. As a result, a semiconductor memory device is obtained which reduces current consumption in the self-refreshing operation by simple control in an internal circuit.

公开(公告)号：US5703522A

公开(公告)日：1997-12-30

申请号：US708429

申请日：1996-09-05

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  G05F3/16 ,  H03K17/16

CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

摘要： A semiconductor circuit or a MOS-DRAM wherein a converter is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converter includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了一种转换器，其在MOS-DRAM的逻辑电路，存储单元和操作电路中的MOS-FET的两个值之间转换衬底电位或体偏置电位，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换器包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

公开(公告)号：US5666315A

公开(公告)日：1997-09-09

申请号：US576351

申请日：1995-12-21

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/83

摘要： In a reading/writing operation, a bit line pair group including a defective memory cell is replaced with a spare bit line pair group. Supply of a precharge potential to a bit line equalize circuit and a power supply interconnection of a sense amplifier is effected by an interconnection V.sub.BLn connected to ground for every bit line pair group. In the replacement of the bit line pair group, supply of a precharge potential to the bit line pair group is cut by a fuse element.

摘要翻译： 在读/写操作中，包括有缺陷存储单元的位线对组被替换为备用位线对组。 为位线均衡电路提供预充电电位和读出放大器的电源互连由每个位线对组连接到地的互连VBLn实现。 在替换位线对组时，通过熔丝元件向位线对组提供预充电电位。