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公开(公告)号：US20070063266A1
公开(公告)日：2007-03-22
申请号：US11520698
申请日：2006-09-14
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/513
摘要： A semiconductor device includes a semiconductor region; a first high dielectric constant insulating film provided on the semiconductor region, the first high dielectric constant insulating film being a film other than alumina; a second high dielectric constant insulating film provided on the first high dielectric constant insulating film, the second high dielectric constant insulating film being an alumina film; and a conductive layer provided on the second high dielectric constant insulating film.
摘要翻译： 半导体器件包括半导体区域; 设置在所述半导体区域上的第一高介电常数绝缘膜，所述第一高介电常数绝缘膜是氧化铝以外的膜; 设置在第一高介电常数绝缘膜上的第二高介电常数绝缘膜，第二高介电常数绝缘膜是氧化铝膜; 以及设置在第二高介电常数绝缘膜上的导电层。
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公开(公告)号：US20070235799A1
公开(公告)日：2007-10-11
申请号：US11763070
申请日：2007-06-14
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US20050212036A1
公开(公告)日：2005-09-29
申请号：US11088947
申请日：2005-03-25
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中以限定多个元件形成区域;浮置栅极，通过第一栅极绝缘膜设置在每个元件形成区域上 ，通过第二栅极绝缘膜设置在浮置栅极上的控制栅极和设置在半导体衬底中的源极/漏极区域，其中至少在第二栅极绝缘膜和控制栅极之间的界面处设置相互扩散层。
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公开(公告)号：US08198159B2
公开(公告)日：2012-06-12
申请号：US12054089
申请日：2008-03-24
IPC分类号： H01L21/324 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US20080176389A1
公开(公告)日：2008-07-24
申请号：US12054089
申请日：2008-03-24
IPC分类号： H01L21/4763
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US07294878B2
公开(公告)日：2007-11-13
申请号：US11088947
申请日：2005-03-25
IPC分类号： H01L27/108
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中以限定多个元件形成区域;浮置栅极，通过第一栅极绝缘膜设置在每个元件形成区域上 ，通过第二栅极绝缘膜设置在浮置栅极上的控制栅极和设置在半导体衬底中的源极/漏极区域，其中至少在第二栅极绝缘膜和控制栅极之间的界面处设置相互扩散层。
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公开(公告)号：US07803682B2
公开(公告)日：2010-09-28
申请号：US11892282
申请日：2007-08-21
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.
摘要翻译： 半导体存储器件包括多个存储晶体管。 每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。 浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和 第一导电膜。 电极间绝缘膜设置在第二导电膜上。 控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。
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公开(公告)号：US07368780B2
公开(公告)日：2008-05-06
申请号：US11763070
申请日：2007-06-14
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US20080054341A1
公开(公告)日：2008-03-06
申请号：US11892282
申请日：2007-08-21
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.
摘要翻译： 半导体存储器件包括多个存储晶体管。 每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。 浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和 第一导电膜。 电极间绝缘膜设置在第二导电膜上。 控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。
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公开(公告)号：US20070284652A1
公开(公告)日：2007-12-13
申请号：US11783141
申请日：2007-04-06
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L29/40117 , H01L29/517
摘要： A semiconductor memory device capable of suppressing detrapping of stored charges from a charge storage dielectric is disclosed. According to one aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor substrate, a blocking dielectric disposed on the semiconductor substrate a charge storage dielectric disposed on the blocking dielectric to store holes, a hole conductive dielectric disposed on the charge storage dielectric, and a gate electrode disposed on the hole conductive dielectric.
摘要翻译： 公开了能够抑制存储电荷从电荷存储电介质中去除的半导体存储器件。 根据本发明的一个方面，提供了一种半导体存储器件，其包括半导体衬底，设置在半导体衬底上的阻挡电介质，设置在阻挡电介质上以存储孔的电荷存储电介质，设置在电荷上的导电电介质 存储电介质和设置在导电电介质上的栅电极。
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