公开(公告)号：US08299523B2

公开(公告)日：2012-10-30

申请号：US13195579

申请日：2011-08-01

申请人： Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

发明人： Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/7811

摘要： In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.

摘要翻译： 通常，根据一个实施例，半导体器件包括第一电极，第一导电类型的第一和第二半导体层，第二导电类型的第三半导体层，第一导电类型的第四半导体层，第一导电类型的第四半导体层 订购。 器件区域包括位于第一沟槽内的栅电极。 具有环形结构的第二沟槽形成穿过第四和第三半导体层的第一区域到第二半导体层，并且包括内部的器件区域和围绕第一区域的第二区域。 第一开口设置在相邻的第一沟槽之间。 具有比第一开口宽的宽度的第二开口设置在装置区域外的第一区域中。 第二电极通过第一和第二开口电连接到第三和第四半导体层。

公开(公告)号：US08144103B2

公开(公告)日：2012-03-27

申请号：US11921444

申请日：2006-06-12

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G2310/0275

摘要： A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.

摘要翻译： 根据本发明的实施例公开了显示装置的驱动电路，在显示装置的显示部分上创建非显示区域，使得部分屏幕显示变得可用。 驱动电路包括移位寄存器和处理从移位寄存器分接的信号的信号处理电路。 在部分屏幕显示中，信号处理电路中断从移位寄存器的预定级分开的信号。 这使得可以实现具有小电路区域的高质量显示的显示装置的驱动电路。

公开(公告)号：US20110141096A1

公开(公告)日：2011-06-16

申请号：US13059775

申请日：2009-05-28

申请人： Yoshimizu Moriya ,  Hiroshi Yoshida ,  Noboru Matsuda

发明人： Yoshimizu Moriya ,  Hiroshi Yoshida ,  Noboru Matsuda

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G02F1/136286 ,  G02F1/13624 ,  G02F2001/13756 ,  G02F2203/03 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0439 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/04 ,  G09G2330/023

摘要： A liquid crystal display device of the present invention includes: an active matrix substrate; a counter substrate; and a liquid crystal layer (512) including light-diffusing liquid crystal that has (i) when no voltage is being applied thereto, a first display state in which the liquid crystal molecules are aligned irregularly, and (ii) when a voltage is being applied, a second display state in which the liquid crystal molecules are aligned regularly, the active matrix substrate having a first surface which is below a surface on which pixel electrodes (504) are provided, the first surface having a first region on which a gap between adjacent pixel electrodes (504) is projected, the first region having partial regions which orthogonally cross gate bus lines GL (501), source bus lines SL (502) being each provided in a second region at a location shifted from a corresponding one of the partial regions so that the source bus line SL (502) is covered by the adjacent pixel electrodes (504).

摘要翻译： 本发明的液晶显示装置包括：有源矩阵基板; 相对基板; 以及包含光扩散液晶的液晶层（512），其具有（i）当不施加电压时，液晶分子不规则地排列的第一显示状态和（ii）当电压为 施加了液晶分子规则排列的第二显示状态，所述有源矩阵基板具有在其上设置有像素电极（504）的表面下方的第一表面，所述第一表面具有第一区域，在所述第一区域上具有间隙 相邻像素电极（504）之间的第一区域被投影，第一区域具有正交交叉栅极总线GL（501）的一部分区域，源极总线SL（502） 部分区域，使得源极总线SL（502）被相邻的像素电极（504）覆盖。

公开(公告)号：US20090027318A1

公开(公告)日：2009-01-29

申请号：US11921444

申请日：2006-06-12

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Noboru Matsuda

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G2310/0275

摘要： A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.

摘要翻译： 根据本发明的实施例公开了显示装置的驱动电路，在显示装置的显示部分上创建非显示区域，使得部分屏幕显示变得可用。 驱动电路包括移位寄存器和处理从移位寄存器分接的信号的信号处理电路。 在部分屏幕显示中，信号处理电路中断从移位寄存器的预定级分开的信号。 这使得可以实现具有小电路区域的高质量显示的显示装置的驱动电路。

公开(公告)号：US07176521B2

公开(公告)日：2007-02-13

申请号：US10834842

申请日：2004-04-30

申请人： Keiko Kawamura ,  Noboru Matsuda ,  Yasuo Ebuchi

发明人： Keiko Kawamura ,  Noboru Matsuda ,  Yasuo Ebuchi

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and cover a plurality of said electrode portions and commonly connected to a plurality of said electrode portions.

摘要翻译： 功率半导体器件包括半导体层; 含多晶硅的栅极; 在所述半导体层的一个表面上形成在所述半导体层中的第一半导体区域，并且可操作地用作源区域和发射极区域中的至少一个; 在所述半导体层的另一个表面上形成在所述半导体层中的第二半导体区域，并且可以用作漏极区域和集电极区域中的至少一个; 通常连接到多个所述栅极并且包括在所述半导体层的平面方向上与其相邻形成的多晶硅部分和金属部分的栅极布线; 形成为覆盖所述第一半导体区域，所述栅极布线布线和多个所述栅极的层间绝缘膜; 形成在所述层间绝缘膜中并与所述第一半导体区连接的电极部; 以及带状电极板，其位于覆盖所述栅极布线线上的所述层间绝缘体并且覆盖多个所述电极部分并且共同连接到多个所述电极部分。

公开(公告)号：US07045858B2

公开(公告)日：2006-05-16

申请号：US10820792

申请日：2004-04-09

申请人： Noboru Matsuda ,  Shoji Takayama ,  Yasuo Ebuchi

发明人： Noboru Matsuda ,  Shoji Takayama ,  Yasuo Ebuchi

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/28052 ,  H01L21/28097 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/7802

摘要： There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.

摘要翻译： 提供了一种半导体器件，其包括第一导电类型的第一半导体层，形成在第一半导体层上的第二导电类型的第二半导体层，第二导电类型不同于第一导电类型，第三半导体层 选择性地形成在第二半导体层上的第一导电类型，通过第三半导体层形成的沟槽和到达第一半导体层的第二半导体层，沿着沟槽的侧表面和底表面形成的栅极电介质膜，以及栅电极 形成为与沟槽的侧表面处的栅极电介质膜接触，与栅极电介质膜接触的表面相对的栅电极的表面以及形成中空部分的沟槽底部的栅极电介质膜 从沟槽的底部延伸到开口侧。

公开(公告)号：US20050199953A1

公开(公告)日：2005-09-15

申请号：US10834842

申请日：2004-04-30

申请人： Keiko Kawamura ,  Noboru Matsuda ,  Yasuo Ebuchi

发明人： Keiko Kawamura ,  Noboru Matsuda ,  Yasuo Ebuchi

IPC分类号： H01L29/78 ,  H01L27/10 ,  H01L29/739

CPC分类号： H01L29/7802 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A power semiconductor device comprises a semiconductor layer; a polysilicon-containing gate; a first semiconductor region formed in said semiconductor layer at one surface of said semiconductor layer and operative to serve as at least one of a source region and an emitter region; a second semiconductor region formed in said semiconductor layer at the other surface of said semiconductor layer and operative to serve as at least one of a drain region and a collector region; a gate routing wire commonly connected to a plurality of said gates and including a polysilicon portion and a metal portion formed adjacent to it in the direction of plane of said semiconductor layer; an interlayer insulator film formed to cover said first semiconductor region, said gate routing wire and a plurality of said gates; an electrode portion formed in said interlayer insulator film and connected to said first semiconductor region; and a strap electrode plate located to cover said interlayer insulator on said gate routing wire and cover a plurality of said electrode portions and commonly connected to a plurality of said electrode portions.

摘要翻译： 功率半导体器件包括半导体层; 含多晶硅的栅极; 在所述半导体层的一个表面上形成在所述半导体层中的第一半导体区域，并且可操作地用作源区域和发射极区域中的至少一个; 在所述半导体层的另一个表面上形成在所述半导体层中的第二半导体区域，并且可以用作漏极区域和集电极区域中的至少一个; 通常连接到多个所述栅极并且包括在所述半导体层的平面方向上与其相邻形成的多晶硅部分和金属部分的栅极布线; 形成为覆盖所述第一半导体区域，所述栅极布线布线和多个所述栅极的层间绝缘膜; 形成在所述层间绝缘膜中并与所述第一半导体区连接的电极部; 以及带状电极板，其位于覆盖所述栅极布线线上的所述层间绝缘体并且覆盖多个所述电极部分并且共同连接到多个所述电极部分。

公开(公告)号：US5057923A

公开(公告)日：1991-10-15

申请号：US503153

申请日：1990-04-02

申请人： Noboru Matsuda

发明人： Noboru Matsuda

IPC分类号： F16D65/09 ,  H04N5/208 ,  H04N5/228 ,  H04N5/262 ,  H04N5/335 ,  H04N5/341 ,  H04N5/357 ,  H04N5/369 ,  H04N5/372 ,  H04N5/378

CPC分类号： H04N5/2628 ,  H04N5/208

摘要： An image pickup device, capable of enlarging images while electronically enlarging the same, picks up images of an object while electronically enlarging the same by two times relative to those in the normal image pickup. In the enlarging image pickup mode, signals having been delayed by a 6H delay circuit are interpolated by a luminance signal interpolating circuit. Horizontal contour of an image based on the interpolated signals is corrected by a horizontal aperture circuit, while vertical contour is corrected by a vertical aperture circuit in response to outputs of the 6H delay circuit. Horizontal contour correcting signals and vertical contour correcting signals are added by an aperture adding circuit. Meanwhile, color-difference signals have their random noises eliminated by a CNR circuit, and are delayed by another 6H delay circuit and interpolated by a color-difference signal interpolating circuit. The interpolated signals are converted by a color-difference signal converting circuit into color-difference signals which are applied to an encoder. For the 6H delay circuit, n/2 CCD 1H delay lines are employed, which can delay the luminance signals or the color-difference signals by n horizontal scanning periods, so that the delay circuit can be reduced in number.