公开(公告)号：US07154798B2

公开(公告)日：2006-12-26

申请号：US11115422

申请日：2005-04-27

申请人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang ,  Fang-Shi Jordan Lai

发明人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang ,  Fang-Shi Jordan Lai

IPC分类号： G11C7/02

CPC分类号： G11C11/1673

摘要： A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.

摘要翻译： 一种用于写入和读取磁存储单元的非破坏性技术和相关阵列，包括对与选择存储器单元相对应的所选读取行的第一信号进行采样，向选择存储单元施加磁场，对所选择的读取的第二信号 并且比较第一和第二信号以确定选择存储器单元的逻辑状态。

公开(公告)号：US20060202254A1

公开(公告)日：2006-09-14

申请号：US11077479

申请日：2005-03-10

申请人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

摘要： A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

公开(公告)号：US07099176B2

公开(公告)日：2006-08-29

申请号：US10827079

申请日：2004-04-19

申请人： Wen Chin Lin ,  Denny D. Tang ,  Li-Shyue Lai

发明人： Wen Chin Lin ,  Denny D. Tang ,  Li-Shyue Lai

IPC分类号： G11C5/08

CPC分类号： G11C11/16

摘要： An MRAM cell including an MRAM cell stack located over a substrate and first and second write lines spanning at least one side of the MRAM cell stack and defining a projected region of intersection of the MRAM cell stack and the first and second write lines. The MRAM cell stack includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer interposing the pinned layer and the free layer. The first write line extends in a first direction within the projected region of intersection. The second write line extends in a second direction within the projected region of intersection. The first and second directions are angularly offset by an angle ranging between 45 and 90 degrees, exclusively. At least one write line may be perpendicular to the easy axis of free layer, while the other line may be rotated off the easy axis of the free layer by an angle which is larger than zero, such as to compensate for a shifting astroid curve.

摘要翻译： MRAM单元包括位于衬底上的MRAM单元堆叠，以及横跨MRAM单元堆叠的至少一侧的第一和第二写入线，并且定义MRAM单元堆叠与第一和第二写入线之间的投影区域。 MRAM单元堆叠包括钉扎层，隧道势垒层和自由层，隧道势垒层插入被钉扎层和自由层。 第一写入线在投影的交叉区域内沿第一方向延伸。 第二写入线在投影的交叉区域内沿第二方向延伸。 第一和第二方向的角度偏移45度到90度之间的角度。 至少一条写入线可以垂直于自由层的容易轴，而另一条线可以从自由层的容易轴旋转大于零的角度，以补偿移动的星形曲线。

公开(公告)号：US20060186440A1

公开(公告)日：2006-08-24

申请号：US11064132

申请日：2005-02-23

申请人： Chao-Hsiung Wang ,  Li-Shyue Lai ,  Denny Tang ,  Wen-Chin Lin

发明人： Chao-Hsiung Wang ,  Li-Shyue Lai ,  Denny Tang ,  Wen-Chin Lin

IPC分类号： H01L29/768

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

摘要： A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode and on the tapered electrode contact surface.

摘要翻译： 提供一种制造存储器件的方法。 该方法包括在衬底上形成电极。 该方法还包括在电极中形成开口以提供靠近开口的锥形电极接触表面。 该方法还包括在电极上和锥形电极接触表面上形成相变特征。

公开(公告)号：US07050290B2

公开(公告)日：2006-05-23

申请号：US10768916

申请日：2004-01-30

申请人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

发明人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

IPC分类号： H01G4/008 ,  H01G4/20

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.

摘要翻译： 实现了具有两个端子的新的电容器装置。 该器件包括覆盖衬底的多个第一导电线。 每个第一导线连接到电容器装置端子之一。 相邻的第一导线连接到相对的端子。 第一导线包括多个导电材料。 多个第二导线覆盖多个第一导线。 每个第二导线连接到电容器件端子中的一个。 相邻的第二导线连接到相对的端子。 覆盖任何第一导线的任何第二导线连接到相对的端子。 第二导线包括多个导电材料。 第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。 第二介电层位于第一导线和第二导线之间。

公开(公告)号：US20050191804A1

公开(公告)日：2005-09-01

申请号：US10791607

申请日：2004-03-01

申请人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

发明人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC分类号： H01L21/00 ,  H01L21/06 ,  H01L21/8234 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

摘要： A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

摘要翻译： 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US20050184282A1

公开(公告)日：2005-08-25

申请号：US10783498

申请日：2004-02-20

申请人： Li-Shyue Lai ,  Denny Tang ,  Wen-chin Lin

发明人： Li-Shyue Lai ,  Denny Tang ,  Wen-chin Lin

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： A phase change memory cell includes a resistive heating element for a phase change body that can expeditiously and efficiently heat a portion of the body with the voltage and current usable with MOSFETs. This is achieved through minimizing the area of an interface between a conductive layer and the body by permitting photolithographic techniques to define one dimension of the interface and thin film deposition techniques to define the other dimension.

摘要翻译： 相变存储单元包括用于相变体的电阻加热元件，其能够利用可用于MOSFET的电压和电流来快速有效地加热身体的一部分。 这通过允许光刻技术限定界面的一个维度和薄膜沉积技术来限定其它尺寸来最小化导电层和主体之间的界面的面积来实现。

公开(公告)号：US20050168914A1

公开(公告)日：2005-08-04

申请号：US10768916

申请日：2004-01-30

申请人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

发明人： Denny Tang ,  Wen-Chin Lin ,  Li-Shyue Lai ,  Chun-Hon Chen ,  Chung-Long Chang

IPC分类号： H01G4/228 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.

摘要翻译： 实现了具有两个端子的新的电容器装置。 该器件包括覆盖衬底的多个第一导电线。 每个第一导线连接到电容器装置端子之一。 相邻的第一导线连接到相对的端子。 第一导线包括多个导电材料。 多个第二导线覆盖多个第一导线。 每个第二导线连接到电容器件端子中的一个。 相邻的第二导线连接到相对的端子。 覆盖任何第一导线的任何第二导线连接到相对的端子。 第二导线包括多个导电材料。 第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。 第二介电层位于第一导线和第二导线之间。

公开(公告)号：US06873535B1

公开(公告)日：2005-03-29

申请号：US10771691

申请日：2004-02-04

申请人： Wen Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang

发明人： Wen Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang

IPC分类号： G11C5/08 ,  H01L21/8246 ,  H01L27/22

CPC分类号： H01L27/228 ,  B82Y10/00

摘要： A magnetic random access memory (MRAM) cell including an MRAM cell stack located over a substrate and first and second write lines spanning opposing termini of the MRAM cell stack. At least one of the first and second write lines includes at least one first portion spanning the MRAM cell stack and at least one second portion proximate the MRAM cell stack. The first and second portions have first and second cross-sectional areas, respectively, wherein the first cross-sectional area is substantially less than the second cross-sectional area.

摘要翻译： 磁性随机存取存储器（MRAM）单元，其包括位于衬底上的MRAM单元堆叠以及横跨MRAM单元堆叠的相对端的第一和第二写入线。 第一和第二写入行中的至少一个包括跨越MRAM单元堆栈的至少一个第一部分和靠近MRAM单元堆栈的至少一个第二部分。 第一和第二部分分别具有第一和第二横截面区域，其中第一横截面面积基本上小于第二横截面面积。