公开(公告)号：US20060202254A1

公开(公告)日：2006-09-14

申请号：US11077479

申请日：2005-03-10

申请人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

摘要： A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

公开(公告)号：US08466505B2

公开(公告)日：2013-06-18

申请号：US11077479

申请日：2005-03-10

申请人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

摘要： A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括栅极结构，其包括在衬底上的隧道氧化物; 隧道氧化物上的浮动栅; 在浮动栅极上的电介质; 以及电介质上的控制栅极。 半导体器件还包括：沿着栅极结构的相对边缘的间隔物; 掺杂有与栅极结构的第一边缘横向间隔开的第一类型掺杂物的第一杂质区; 以及掺杂有与第一类型相反的第二类型掺杂剂的第二杂质区，漏极基本上在漏极间隔下方并且基本上与栅极结构的第二边缘对准。

公开(公告)号：US20060125121A1

公开(公告)日：2006-06-15

申请号：US11081416

申请日：2005-03-16

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC分类号： H01L31/109

CPC分类号： H01L27/095 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/812

摘要： A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 Å. Interfacial layers are formed between the first and the second Schottky barrier regions.

摘要翻译： 一种基于隧道注入的肖特基源/漏存储单元，包括：第一半导体层，其具有覆盖绝缘层的第一导电类型，其中所述第一半导体作为体区; 覆盖半导体层的栅极电介质; 覆盖栅极电介质的栅电极; 栅电极侧面的一对间隔物; 以及形成在源区域上的第一肖特基势垒结和形成在身体区域的相对侧上的漏极区域上的第二肖特基势垒结。 源极和区域与栅电极具有重叠部分，并且重叠部分的长度优选大于约。 在第一和第二肖特基势垒区之间形成界面层。

公开(公告)号：US20070052027A1

公开(公告)日：2007-03-08

申请号：US11220176

申请日：2005-09-06

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L27/01

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

摘要翻译： 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 代表了包含{l，m，n}的米勒指数族，其中l 2+ + m 2 + 2 + 2 2 / 2 + 2＆lt; 2＆gt; 2＆gt; 2＆lt; 2＆gt; 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US07737532B2

公开(公告)日：2010-06-15

申请号：US11220176

申请日：2005-09-06

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

摘要翻译： 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 表示包括{l，m，n}的米勒指数族，其中l2 + m2 + n2> i2 + j2 + k2。 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US20060091490A1

公开(公告)日：2006-05-04

申请号：US11077478

申请日：2005-03-10

申请人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

发明人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC分类号： H01L31/105

CPC分类号： H01L29/7391 ,  H01L29/868

摘要： A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and the gate electrode; a source doped with a first type of dopant substantially under the source gate spacer wherein the source has a horizontal distance from a first edge of the gate electrode; a drain doped with the opposite type of the source substantially under the drain spacer and substantially aligned horizontally with a second edge of the gate electrode; a source silicide adjacent the source; and a drain silicide adjacent the drain.

摘要翻译： 门式p-i-n二极管及其形成方法。 门控p-i-n二极管包括：半导体衬底; 半导体衬底上的栅极电介质; 栅电极上的栅电极; 源栅极间隔物和漏极栅极间隔物，沿着栅极电介质和栅电极的相应边缘; 源极掺杂有基本上在源栅极间隔物下方的第一类型掺杂剂的源，其中源极与栅电极的第一边缘具有水平距离; 基本上在所述漏极间隔物的下方掺杂有相反类型的源极的漏极，并且与所述栅极电极的第二边缘基本对准; 邻近源极的源硅化物; 和漏极附近的漏极硅化物。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20110223727A1

公开(公告)日：2011-09-15

申请号：US13113530

申请日：2011-05-23

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

摘要翻译： 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US07803718B2

公开(公告)日：2010-09-28

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L23/31

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。