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1.发明授权公开(公告)号：US07154798B2
公开(公告)日：2006-12-26
申请号：US11115422
申请日：2005-04-27
IPC分类号： G11C7/02
CPC分类号： G11C11/1673
摘要： A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.
摘要翻译： 一种用于写入和读取磁存储单元的非破坏性技术和相关阵列，包括对与选择存储器单元相对应的所选读取行的第一信号进行采样，向选择存储单元施加磁场，对所选择的读取的第二信号 并且比较第一和第二信号以确定选择存储器单元的逻辑状态。
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公开(公告)号：US20120212359A1
公开(公告)日：2012-08-23
申请号：US13029754
申请日：2011-02-17
申请人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
发明人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.
摘要翻译： 模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。 每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。 比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。 基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。 通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。
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公开(公告)号：US07511988B2
公开(公告)日：2009-03-31
申请号：US11483819
申请日：2006-07-10
申请人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
发明人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
CPC分类号： G11C11/4125
摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.
摘要翻译： 静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。 开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。
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公开(公告)号：US08416105B2
公开(公告)日：2013-04-09
申请号：US13029754
申请日：2011-02-17
申请人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
发明人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.
摘要翻译： 模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。 每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。 比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。 基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。 通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。
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公开(公告)号：US08279097B2
公开(公告)日：2012-10-02
申请号：US12775104
申请日：2010-05-06
IPC分类号： H03M1/10
CPC分类号： H03M1/1042 , H03M1/1004 , H03M1/168
摘要： A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.
摘要翻译： 一种操作模数转换器（ADC）的方法包括提供包括多个级的ADC，每个级分别包括运算放大器，以及分别包括第一输入端和第二输入端的第一电容器和第二电容器 。 第一电容器和第二电容器中的每一个包括连接到运算放大器的相同输入端的附加端。 该方法还包括执行多个信号转换。 每个信号转换在多级中的一个级的放大阶段中包括将第一电压施加到多级中的一级的第一输入端，从两个不同电压随机选择第二电压; 以及将所述第二电压施加到所述多个级中的所述一个级的所述第二输入端。
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公开(公告)号：US20110092041A1
公开(公告)日：2011-04-21
申请号：US12969342
申请日：2010-12-15
申请人： Fang-Shi Jordan Lai , ChiaHua Ho , Fu-Liang Yang
发明人： Fang-Shi Jordan Lai , ChiaHua Ho , Fu-Liang Yang
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L21/76224 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type.
摘要翻译： 集成电路结构包括半导体衬底; 二极管 以及与二极管电连接的相变元件。 二极管包括第一导电类型的第一掺杂半导体区域，其中第一掺杂半导体区域嵌入在半导体衬底中; 以及在所述第一掺杂半导体区域之上并与其邻接的第二掺杂半导体区域，其中所述第二掺杂半导体区域是与所述第一导电类型相反的第二导电类型。
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公开(公告)号：US20110012763A1
公开(公告)日：2011-01-20
申请号：US12775104
申请日：2010-05-06
CPC分类号： H03M1/1042 , H03M1/1004 , H03M1/168
摘要： A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.
摘要翻译： 一种操作模数转换器（ADC）的方法包括提供包括多个级的ADC，每个级分别包括运算放大器，以及分别包括第一输入端和第二输入端的第一电容器和第二电容器 。 第一电容器和第二电容器中的每一个包括连接到运算放大器的相同输入端的附加端。 该方法还包括执行多个信号转换。 每个信号转换在多级中的一个级的放大阶段中包括将第一电压施加到多级中的一级的第一输入端，从两个不同电压随机选择第二电压; 以及将所述第二电压施加到所述多个级中的所述一个级的所述第二输入端。
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公开(公告)号：US08928508B2
公开(公告)日：2015-01-06
申请号：US13526147
申请日：2012-06-18
CPC分类号： H03M1/1009 , H03M1/1004 , H03M1/365
摘要： An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.
摘要翻译： 包括连接到ADC的多个比较器的模数转换器（ADC）。 ADC还包括连接到多个比较器中的每一个的第一对端子和第二对端子。 ADC还包括耦合到第一对端子中的每一个的第一对开关和耦合到第二对端子中的每一个的第二对开关，其中第一和第二对开关被配置为在 正常操作和校准配置。 如果对应的比较器被配置为校准，则比较器对应的比较器被配置为正常运行。
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公开(公告)号：US08228221B2
公开(公告)日：2012-07-24
申请号：US12891952
申请日：2010-09-28
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M3/02
摘要： In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.
摘要翻译： 在将模拟信号转换为数字格式的方法中，使用Σ-Δ调制接收和处理模拟输入信号，以提供表示数字格式的模拟输入信号的第一数字信号，并提供表示第 在Σ-Δ调制期间引入的第一个误差。 估计在Σ-Δ调制期间引入误差的第二个误差。 基于第一和第二数字信号确定预校正信号。 确定估计的第二误差和预校正数字信号之间的差异以提供表示数字格式的模拟输入信号的数字输出信号。 控制基于模拟输入信号，数字输出信号和第二数字信号来调整数字输出信号的纠错元件。
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公开(公告)号：US20100164766A1
公开(公告)日：2010-07-01
申请号：US12347014
申请日：2008-12-31
IPC分类号： H03M1/10
CPC分类号： H03M1/1057
摘要： A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.
摘要翻译： 提供了一种校准数模转换器（DAC）的方法。 DAC包括最低有效位（LSB）块和与LSB块相邻的虚拟LSB块。 DAC具有最高有效位（MSB）块，其中包含MSB温度计宏。 该方法包括测量虚拟LSB块以获得虚拟LSB和; 并校准MSB块，使得每个MSB温度计宏提供与虚拟LSB总和大致相同的电流。
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