公开(公告)号：US06340898B1

公开(公告)日：2002-01-22

申请号：US08993122

申请日：1997-12-18

Applicant: Pierre Haubursin ,  Ching Yu

Inventor： Pierre Haubursin ,  Ching Yu

IPC: H03K19173

CPC classification number: H03K19/1731

Abstract: An output driver that may be configured to operate as a totem-pole driver, or as an open-drain driver. The output driver comprises a totem-pole driver coupled to an output pin. A control circuit is coupled to the output enable input of the totem-pole driver. The control circuit is supplied with an open-drain control signal controlled by the user interface. When the open-drain control signal is at a first logic level, the output driver operates as an open-drain driver. When the open-drain control signal is at a second logic level, the output driver is configured to operate as a totem-pole driver.

Abstract translation: 可以配置为作为图腾柱驱动器或作为开漏驱动器运行的输出驱动器。 输出驱动器包括耦合到输出引脚的图腾柱驱动器。 控制电路耦合到图腾柱驱动器的输出使能输入。 该控制电路具有由用户接口控制的开漏控制信号。 当开漏控制信号处于第一逻辑电平时，输出驱动器作为开漏驱动器工作。 当开漏控制信号处于第二逻辑电平时，输出驱动器被配置为作为图腾柱驱动器工作。

公开(公告)号：US06317847B1

公开(公告)日：2001-11-13

申请号：US09144644

申请日：1998-08-31

Applicant: Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

Inventor： Pierre F. Haubursin ,  Ching Yu ,  Din-I Tsai ,  David Balmforth

IPC: G06F1100

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3648

Abstract: A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Abstract translation: 在网络接口中提供了用于跟踪对所选寄存器的读和写访问的系统。 该系统具有一个读取跟踪寄存器，每个寄存器包含一个独立的位，用于监视外部CPU进行读取访问。 写入跟踪寄存器为每个待监视的寄存器提供一个位，以便CPU进行写访问。 当CPU对被监视的寄存器执行读或写访问时，从CPU解码地址信号的解码器产生提供给读跟踪寄存器和/或写跟踪寄存器的跟踪选择信号。 响应于跟踪选择信号，表示被监视寄存器的位被设置为预定的逻辑状态，指示所监视的寄存器被CPU访问以用于读取和/或写入。

公开(公告)号：US06229817B1

公开(公告)日：2001-05-08

申请号：US08993127

申请日：1997-12-18

Applicant: Jenny Liu Fischer ,  Ching Yu ,  Jeffrey Dwork

Inventor： Jenny Liu Fischer ,  Ching Yu ,  Jeffrey Dwork

IPC: G06F1516

CPC classification number: H04L12/40032 ,  H04L12/413

Abstract: A system for adjusting late collision slot time is provided in a network interface having a media access control (MAC) engine that performs collision detection. The MAC engine comprises a MAC transmit block that transmits frames via a media independent interface (MII) to an ektemal physical layer device (PHY) coupled to the MII, and a MAC receive block for receiving frames from the PHY. A MAC control register is configured for storing ablate collision time slot adjustment value used to adjust the late collision slot time. The late collision time slot adjustment value is programmed to compensate for variations in internal delays of PHYs that may be connected to the MII.

Abstract translation: 在具有执行冲突检测的媒体访问控制（MAC）引擎的网络接口中提供了一种用于调整后期冲突时隙时间的系统。 MAC引擎包括通过媒体独立接口（MII）向耦合到MII的物理层设备（PHY）发送帧的MAC传输块，以及用于从PHY接收帧的MAC接收块。 配置MAC控制寄存器，用于存储用于调整后期冲突时隙时间的切换冲突时隙调整值。 后期冲突时隙调整值被编程以补偿可能连接到MII的PHY的内部延迟的变化。

公开(公告)号：US5966421A

公开(公告)日：1999-10-12

申请号：US989435

申请日：1997-12-12

Applicant: Pierre Haubursin ,  Ching Yu

Inventor： Pierre Haubursin ,  Ching Yu

IPC: H03K21/00 ,  H03K23/66

CPC classification number: H03K23/66 ,  H03K21/00

Abstract: An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

Abstract translation: 计数到给定中心时钟频率FC的期望时钟频率FD的m位计数器由两个子计数器的链模拟。 中心时钟频率FC在期望时钟频率FD上的比率r被推定为r = FC / FD = 2n * p，其中n是零或整数之一（即，0,1,2,3，...， ），其中p是整数。 1到p个子计数器从1到p由中央时钟频率FC驱动。 1到p计数器的输出是一个中间时钟频率，每个周期性计数从1到p包括一个脉冲。 中间时钟频率驱动m + n位子计数器，附加n位作为m + n位子计数器的最低有效位。 以这种方式，m + n位子计数器的m个最高有效位计数到期望的时钟频率FD。

公开(公告)号：US5938728A

公开(公告)日：1999-08-17

申请号：US961190

申请日：1997-10-30

Applicant: Jeffrey Roy Dwork ,  Ching Yu ,  Robert Alan Williams ,  Rajat Roy

Inventor： Jeffrey Roy Dwork ,  Ching Yu ,  Robert Alan Williams ,  Rajat Roy

IPC: G06F1/24 ,  G06F1/12 ,  G06F13/00 ,  G06F13/12 ,  H03K17/22 ,  H04L29/10

CPC classification number: G06F1/24

Abstract: A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables the network interface device to initialize upon power up and start to monitor network media for wakeup traffic indicating the host computer in the workstation should be activated.

Abstract translation: 一种用于工作站的网络接口，被配置为在网络接口保持处于上电状态时被关闭到待机模式，该旁路电路被配置为使网络接口中的配置寄存器能够完成对已知的配置信息的加载 状态，而不管在初始化间隔期间是否存在来自网络的外部数据时钟。 旁路电路确保需要网络时钟（例如，发送时钟或接收时钟）的网络接口中的配置寄存器被保持在已知状态，以使得能够独立地初始化网络接口。 旁路电路的一个示例保持上电复位信号，直到在预定数量的检测到的时钟周期内检测到必要的网络时钟信号。 旁路电路的另一个例子是响应于上电复位信号而将不存在的时钟信号替换为独立的时钟源，并将上电复位信号保持预定数量的独立时钟周期，随后切换回提供 所需的时钟信号。 所公开的布置使得网络接口设备能够在上电时进行初始化，并开始监视网络媒体的唤醒流量，指示工作站中的主计算机应被激活。

公开(公告)号：US5835719A

公开(公告)日：1998-11-10

申请号：US972093

申请日：1997-11-17

Applicant: Glen Gibson ,  Thomas J. Runaldue ,  Ching Yu

Inventor： Glen Gibson ,  Thomas J. Runaldue ,  Ching Yu

IPC: G06F1/32 ,  H04L12/12 ,  G06F13/38

CPC classification number: G06F1/3209 ,  H04L12/12 ,  Y02B60/32 ,  Y02B60/34

Abstract: An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.

Abstract translation: 公开了一种用于在具有互连网络（例如，路由器互连LAN）的数据交换系统内远程唤醒预期节点的装置和方法。 公开了一种唤醒命令格式，其中对应于预期节点的地址的序列通过从远程源节点发送的一个或多个分组的相应数据字段被广泛地连续N次（例如，至少16个连续时间） 到目标节点。 当预期节点处于睡眠模式时，当预定节点接收到该特定序列时，响应地启动唤醒操作，使得休眠节点至少在一段时间内唤醒以响应未来接收到的分组。

公开(公告)号：US08959095B2

公开(公告)日：2015-02-17

申请号：US13162421

申请日：2011-06-16

Applicant: Steve L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

Inventor： Steve L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Ching Yu ,  John Mingyung Chiang ,  Der-Ren Chu

IPC: G06F17/30 ,  H04L12/747 ,  H04L12/741 ,  H04L12/861 ,  H04L29/06 ,  H04L12/851 ,  H04L12/863

CPC classification number: G06F17/30867 ,  G06F17/30864 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/621 ,  H04L49/90 ,  H04L67/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162 ,  H04L69/163 ,  H04L69/164 ,  H04L69/22 ,  Y10S707/922

Abstract: Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

Abstract translation: 大致描述了网络接口设备被分配最大的搜索范围。 散列函数被应用于每个输入分组的报头信息，以产生分组的哈希码。 哈希代码指定在其中应当找到特定头部信息的表的特定子集，并且在该子集内进行迭代搜索。 如果搜索在超出搜索限制之前找到匹配的条目，则传入数据包将被传递到匹配条目中标识的接收队列。 但是，如果在找到匹配的条目之前搜索达到搜索限制，则设备会将数据包传递到主机系统中的默认队列（如内核队列）。 然后，内核负责将数据包传递到正确的端点。

公开(公告)号：US20140059221A1

公开(公告)日：2014-02-27

申请号：US13765579

申请日：2013-02-12

Applicant: Steve L. Pope ,  David J. Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve L. Pope ,  David J. Riddoch ,  Ching Yu ,  Derek Roberts

IPC: H04L29/06 ,  H04L12/863

CPC classification number: H04L63/10 ,  H04L47/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9063

Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

Abstract translation: 大体上描述了一种从计算设备接收数据包以便传输到网络上的网络接口设备，具有一定特性的数据分组仅在发送队列具有发送具有该特性的分组的权限时发送分组。 数据包特征可以包括传输协议号，源和目的端口号，源和目的IP地址。 基于建立队列的进程的权限级别，可以通过内核例程在建立传输队列时将授权编程到NIC中。 以这种方式，用户进程可以使用不受信任的用户级协议栈来发起到网络上的数据传输，而NIC保护系统或网络的其余部分免受某些种类的折中。

公开(公告)号：US08483347B2

公开(公告)日：2013-07-09

申请号：US11733248

申请日：2007-04-10

Applicant: Norman R. Singleton ,  David A. Altman ,  Ching Yu ,  James A. Rex ,  David R. Forsyth

Inventor： Norman R. Singleton ,  David A. Altman ,  Ching Yu ,  James A. Rex ,  David R. Forsyth

IPC: G21C1/04

CPC classification number: G21C13/02 ,  G21Y2002/201 ,  G21Y2002/301 ,  G21Y2002/402 ,  G21Y2004/30 ,  Y02E30/40

Abstract: In a pressurized water reactor with all of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.

Abstract translation: 在具有所有核心仪器的压水反应器中，通过反应器头部进入核心，将引入仪器的每个燃料组件与上部内部仪器仪表导轨对准。 在上部内部上部支撑组件上方的高度中，仪器由作为仪表导向器一部分的上部安装的仪表柱保护和对准，并且从上部支撑组件朝向反应器头部以色调以相应的头部穿透延伸。 上部安装的仪器支架在一端通过上导向管横向支撑，另一端由上支撑板支撑。

公开(公告)号：US07831749B2

公开(公告)日：2010-11-09

申请号：US11050474

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F3/00

CPC classification number: G06F9/4812 ,  G06F13/28 ,  G06F13/32 ,  G06F13/385

Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

Abstract translation: 大体描述了用于管理主机子系统和网络接口设备之间的数据传输的方法，其中主机将数据缓冲器描述符写入DMA描述符队列，并且网络接口设备写入完成事件以在主机完成处理 数据缓冲区。 每个完成事件描述符通知主机NIC和一个或多个数据缓冲区之间的数据传输完成，并且还可以在完成事件中嵌入队列空通知。