公开(公告)号：US08481142B1

公开(公告)日：2013-07-09

申请号：US11215845

申请日：2005-08-30

申请人： Thanas Budri ,  Thomas Francis ,  David Tucker ,  Stephen W. Swan ,  Sergei Drizlikh

发明人： Thanas Budri ,  Thomas Francis ,  David Tucker ,  Stephen W. Swan ,  Sergei Drizlikh

IPC分类号： H01L21/302

CPC分类号： G01N23/223 ,  G01N2223/076 ,  H01L21/32136 ,  H01L22/12 ,  Y10T428/234

摘要： A system and method for monitoring chloride content and concentration induced by a metal etch process is disclosed. A blank metal film is deposited on a semiconductor wafer. A metal etch process is then applied to partially etch the blank metal film on the wafer. The metal etch process exposes the metal film to chlorine. The wafer is then scanned using surface profiling total X-ray reflection fluorescence. A chlorine concentration map is generated that shows quantitative and spatial information about the chlorine on the wafer. Information from the chlorine concentration map is then used to select a value of chlorine concentration for a metal etch process that will not create metal chloride corrosion on a semiconductor wafer.

摘要翻译： 公开了一种用于监测由金属蚀刻工艺引起的氯化物含量和浓度的系统和方法。 空白金属膜沉积在半导体晶片上。 然后施加金属蚀刻工艺以部分地蚀刻晶片上的空白金属膜。 金属蚀刻工艺将金属膜暴露于氯。 然后使用表面形貌总X射线反射荧光扫描晶片。 产生氯浓度图，其显示关于晶片上的氯的定量和空间信息。 然后使用来自氯浓度图的信息来选择不会在半导体晶片上产生金属氯化物腐蚀的金属蚀刻工艺的氯浓度值。

公开(公告)号：US08476934B2

公开(公告)日：2013-07-02

申请号：US13188243

申请日：2011-07-21

申请人： Arlo J. Aude ,  Soumya Chandramouli

发明人： Arlo J. Aude ,  Soumya Chandramouli

IPC分类号： H03K5/22

CPC分类号： H04L25/0274 ,  H04L25/06

摘要： Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.

摘要翻译： 具有集成参考电压的差分信号检测电路。 参考电压作为输出电压的偏移量相加，其积分可确保参考电压的变化密切跟踪信号的变化。 因此，正在检测的信号的检测阈值在电路制造过程，电源电压和工作温度的变化方面保持更一致。

公开(公告)号：US08476878B2

公开(公告)日：2013-07-02

申请号：US12946158

申请日：2010-11-15

申请人： Siew K. Hoon ,  Mengzhe Ma

发明人： Siew K. Hoon ,  Mengzhe Ma

IPC分类号： G05F1/59

CPC分类号： H02M1/36

摘要： A startup circuit for use in a DC-DC converter having an input voltage terminal and an output voltage terminal, with the output voltage terminal connected to an output capacitor and with said converter including a pass transistor for transferring charge from the input terminal to the output terminal. The startup circuit includes a control circuit configured to cause the pass transistor to conduct an output current during start up when the output terminal voltage is approaching a final regulated voltage, with the output current being comprised of first and second current components, with the first current component being proportional to the output voltage and the second current component being proportional to the input voltage, with the two components being combined so as to resist changes in the power dissipation in the pass transistor during startup.

摘要翻译： 一种用于具有输入电压端子和输出电压端子的DC-DC转换器的启动电路，其输出电压端子连接到输出电容器，并且所述转换器包括用于将电荷从输入端子传输到输出端的传输晶体管 终奌站。 启动电路包括控制电路，其被配置为当输出端电压接近最终调节电压时使得通过晶体管在启动期间传导输出电流，其中输出电流由第一和第二电流分量组成，其中第一电流 分量与输出电压成比例，并且第二电流分量与输入电压成比例，其中两个分量被组合以便抵抗启动期间传输晶体管中功率耗散的变化。

公开(公告)号：US08447000B2

公开(公告)日：2013-05-21

申请号：US12319985

申请日：2009-01-12

申请人： Tulsi Manickam ,  Peter J. Sallaway ,  Sreen A. Raghavan ,  Abhijit M. Phanse ,  James B. Wieser

发明人： Tulsi Manickam ,  Peter J. Sallaway ,  Sreen A. Raghavan ,  Abhijit M. Phanse ,  James B. Wieser

IPC分类号： H04B1/10 ,  H04B15/00

CPC分类号： H04L25/03057 ,  H04L25/03254

摘要： A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.

摘要翻译： 提出了一种容易从具有长电缆长度的传输通道接收信号的接收机。 接收机包括一个模拟预滤波器，用于消除来自预定传输信道的失真和符号间干扰。 模拟预滤波器与提供数字均衡的数字接收机耦合。 模拟均衡与数字均衡的组合允许简化的数字均衡，同时保持数字信号处理的通用性。

公开(公告)号：US20130093478A1

公开(公告)日：2013-04-18

申请号：US13272217

申请日：2011-10-13

申请人： KERN WAI WONG

发明人： KERN WAI WONG

IPC分类号： H03L7/08

CPC分类号： H04B1/7087 ,  H03L7/0995 ,  H03L7/235 ,  H04B1/7073 ,  H04B1/7156 ,  H04B15/04

摘要： A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

公开(公告)号：US20130088171A1

公开(公告)日：2013-04-11

申请号：US13267156

申请日：2011-10-06

申请人： David James Fensore

发明人： David James Fensore

IPC分类号： H05B37/02

CPC分类号： H05B33/0818 ,  H05B33/0827 ,  Y02B20/347

摘要： A device driver which includes an input driver configured to produce a sequence of uncompensated drive signals along with compensation circuitry connected to receive the uncompensated drive signals and to produce corresponding compensated drive signals. The compensation circuitry is capable of storing two or less control points that define a single compensation curve such as a Bezier curve, with the compensation circuitry converting the uncompensated drive signals to the corresponding compensated drive signals utilizing the control points. An output driver is configured to drive a device such as one or more light emitting diodes to be connected to the output driver with the compensated drive signals.

摘要翻译： 一种设备驱动器，其包括输入驱动器，其被配置为产生一系列未补偿的驱动信号以及连接以接收未补偿的驱动信号并产生相应的经补偿的驱动信号的补偿电路。 补偿电路能够存储限定单个补偿曲线（例如贝塞尔曲线）的两个或更少控制点，补偿电路利用控制点将未补偿的驱动信号转换成相应的补偿驱动信号。 输出驱动器被配置为驱动诸如一个或多个发光二极管的装置以经补偿的驱动信号连接到输出驱动器。

公开(公告)号：US08417367B1

公开(公告)日：2013-04-09

申请号：US10920834

申请日：2004-08-18

申请人： George Logsdon ,  Ramesh Rao ,  Teresa Colpaert ,  Michael A. Hart

发明人： George Logsdon ,  Ramesh Rao ,  Teresa Colpaert ,  Michael A. Hart

IPC分类号： G06F19/00

CPC分类号： G06Q10/06

摘要： A manufacturing exception handling system is described for use with a manufacturing execution system that controls a semiconductor manufacturing process. The present invention provides real time information to the user that identifies restrictions that have been placed on the use of entities and inventories in the semiconductor manufacturing process. The present invention also provides real time information to the user that identifies the persons who are authorized to remove the restrictions. The present invention saves the time and effort that would otherwise be required to find out why a restriction existed and who could remove the restriction during the semiconductor manufacturing process.

摘要翻译： 描述了与控制半导体制造过程的制造执行系统一起使用的制造异常处理系统。 本发明向用户提供识别在半导体制造过程中对实体和库存的使用的限制的实时信息。 本发明还向用户提供识别被授权去除限制的人的实时信息。 本发明节省了为了找出限制的原因而需要的时间和精力，以及谁可以在半导体制造过程中消除限制。

公开(公告)号：US08416173B2

公开(公告)日：2013-04-09

申请号：US11470247

申请日：2006-09-05

申请人： Christopher A. Ludden

发明人： Christopher A. Ludden

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0224 ,  G09G2310/0289 ,  G09G2330/021

摘要： A method is arranged to process a frame for an LCD with a modified polarity pattern. The pattern employs a polarity reversal scheme that results in line inversion and/or dot inversion patterns that are observable by pixel locations within the frame. The drive polarity for the column drivers in the LCD is toggled according to the modified polarity pattern. The scanning sequence for each row on the display is modified for cooperation with the pattern. A first subframe is scanned during a first interval while applying a first set of drive polarities. A second subframe is scanned during a second interval that is non-overlapping with the first time interval. The application of the method enables the column drivers in the LCD to operate with reduced power while retaining the benefits of line and dot inversion techniques.

摘要翻译： 一种用于处理具有修改的极性图案的LCD的框架的方法。 该模式采用极性反转方案，其导致由框架内的像素位置可观察到的线反转和/或点反转模式。 LCD中的列驱动器的驱动极性根据修改的极性模式切换。 修改显示器上每一行的扫描顺序，以与图案协作。 在施加第一组驱动极性的同时，在第一间隔期间扫描第一子帧。 在与第一时间间隔不重叠的第二间隔期间扫描第二子帧。 该方法的应用使得LCD中的列驱动器能够以较低的功率运行，同时保留了线和点反转技术的优点。

公开(公告)号：US08401504B2

公开(公告)日：2013-03-19

申请号：US12759568

申请日：2010-04-13

申请人： Michael Hendrikus Laurentius Kouwenhoven

发明人： Michael Hendrikus Laurentius Kouwenhoven

IPC分类号： H04B1/10

CPC分类号： G06G7/16 ,  G01R19/02 ,  G01R19/22 ,  H04B1/30

摘要： Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals.

摘要翻译： 这里描述的是减少RMS-DC转换器中的偏移误差的技术。 该技术涉及分别产生具有第一和第二反馈路径的第一和第二反馈信号。 然后采用乘法器来接收第一和第二信号，并且基于乘以第一信号和第二信号来提供第三信号。 第一信号基于输入信号和第一反馈信号，第二信号基于输入信号和第二反馈信号。 然后使用斩波器接收基于第三信号的输出信号和斩波信号，并且进而基于将输出信号与斩波信号相乘来提供第四信号。 结果，第四信号表示被转换到与第一和第二信号的低频噪声分量不同的频率的输出信号。

公开(公告)号：US08395427B1

公开(公告)日：2013-03-12

申请号：US12973323

申请日：2010-12-20

申请人： Xiang Gao ,  Ahmad Bahai ,  Mounir Bohsali ,  Ali Djabbari ,  Eric Klumperink ,  Bram Nauta ,  Gerard Socci

发明人： Xiang Gao ,  Ahmad Bahai ,  Mounir Bohsali ,  Ali Djabbari ,  Eric Klumperink ,  Bram Nauta ,  Gerard Socci

IPC分类号： H03L7/06

CPC分类号： H03L7/091

摘要： Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

摘要翻译： 控制电路和控制采样锁相环（PLL）的方法。 通过控制一个或多个采样控制信号的占空比，可以减少参考信号缓冲器的功率消耗和被控制的采样PLL的杂散输出信号。